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PIC16C5X Data Sheet
EPROM/ROM-Based 8-bit CMOS Microcontroller Series
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D
Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
* * *
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS30453D - page ii
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
EPROM/ROM-Based 8-bit CMOS Microcontroller Series
Devices Included in this Data Sheet:
* * * * * * * * * PIC16C54 PIC16CR54 PIC16C55 PIC16C56 PIC16CR56 PIC16C57 PIC16CR57 PIC16C58 PIC16CR58 Note: PIC16C5X refers to all revisions of the part (i.e., PIC16C54 refers to PIC16C54, PIC16C54A, and PIC16C54C), unless specifically called out otherwise. * * * * * 12-bit wide instructions 8-bit wide data path Seven or eight special function hardware registers Two-level deep hardware stack Direct, indirect and relative addressing modes for data and instructions
Peripheral Features:
* 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler * Power-on Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable Code Protection * Power saving SLEEP mode * Selectable oscillator options: - RC: Low cost RC oscillator - XT: Standard crystal/resonator - HS: High speed crystal/resonator - LP: Power saving, low frequency crystal
High-Performance RISC CPU:
* Only 33 single word instructions to learn * All instructions are single cycle except for program branches which are two-cycle * Operating speed: DC - 40 MHz clock input DC - 100 ns instruction cycle Device PIC16C54 PIC16C54A PIC16C54C PIC16CR54A PIC16CR54C PIC16C55 PIC16C55A PIC16C56 PIC16C56A PIC16CR56A PIC16C57 PIC16C57C PIC16CR57C PIC16C58B PIC16CR58B Pins 18 18 18 18 18 28 28 18 18 18 28 28 28 18 18 I/O 12 12 12 12 12 20 20 12 12 12 20 20 20 12 12 EPROM/ RAM ROM 512 512 512 512 512 512 512 1K 1K 1K 2K 2K 2K 2K 2K 25 25 25 25 25 24 24 25 25 25 72 72 72 73 73
CMOS Technology:
* Low power, high speed CMOS EPROM/ROM technology * Fully static design * Wide operating voltage and temperature range: - EPROM Commercial/Industrial 2.0V to 6.25V - ROM Commercial/Industrial 2.0V to 6.25V - EPROM Extended 2.5V to 6.0V - ROM Extended 2.5V to 6.0V * Low power consumption - < 2 mA typical @ 5V, 4 MHz - 15 A typical @ 3V, 32 kHz - < 0.6 A typical standby current (with WDT disabled) @ 3V, 0C to 70C Note: In this document, figure and table titles refer to all varieties of the part number indicated, (i.e., The title "Figure 15-1: Load Conditions For Device Timing Specifications - PIC16C54A", also refers to PIC16LC54A and PIC16LV54A parts), unless specifically called out otherwise.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 1
PIC16C5X
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
RA2 RA3 T0CKI MCLR/VPP VSS RB0 RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PDIP, SOIC, Windowed CERDIP
T0CKI VDD N/C VSS N/C RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5
PIC16C54 PIC16CR54 PIC16C56 PIC16CR56 PIC16C58 PIC16CR58
PIC16C55 PIC16C57 PIC16CR57
SSOP
RA2 RA3 T0CKI MCLR/VPP VSS VSS RB0 RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
SSOP
VSS T0CKI VDD VDD RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 VSS *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5
Device Differences
Device PIC16C54 PIC16C54A PIC16C54C PIC16C55 PIC16C55A PIC16C56 PIC16C56A PIC16C57 PIC16C57C PIC16C58B PIC16CR54A PIC16CR54C PIC16CR56A PIC16CR57C PIC16CR58B Voltage Range 2.5-6.25 2.0-6.25 2.5-5.5 2.5-6.25 2.5-5.5 2.5-6.25 2.5-5.5 2.5-6.25 2.5-5.5 2.5-5.5 2.5-6.25 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 Oscillator Selection (Program) Factory User User Factory User Factory User Factory User User Factory Factory Factory Factory Factory Oscillator See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 See Note 1 Process Technology (Microns) 1.2 0.9 0.7 1.7 0.7 1.7 0.7 1.2 0.7 0.7 1.2 0.7 0.7 0.7 0.7 ROM Equivalent PIC16CR54A -- PIC16CR54C -- -- -- PIC16CR56A -- PIC16CR57C PIC16CR58B N/A N/A N/A N/A N/A MCLR Filter No No Yes No Yes No Yes No Yes Yes Yes Yes Yes Yes Yes
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties, please refer to Section 2.0.
PIC16C54 PIC16CR54 PIC16C56 PIC16CR56 PIC16C58 PIC16CR58
PIC16C55 PIC16C57 PIC16CR57
DS30453D-page 2
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5 2.0 PIC16C5X Device Varieties ......................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................ 9 4.0 Oscillator Configurations ............................................................................................................................................................ 15 5.0 Reset .......................................................................................................................................................................................... 19 6.0 Memory Organization ................................................................................................................................................................. 25 7.0 I/O Ports ..................................................................................................................................................................................... 35 8.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 37 9.0 Special Features of the CPU...................................................................................................................................................... 43 10.0 Instruction Set Summary ............................................................................................................................................................ 49 11.0 Development Support................................................................................................................................................................. 61 12.0 Electrical Characteristics - PIC16C54/55/56/57 ......................................................................................................................... 67 13.0 Electrical Characteristics - PIC16CR54A ................................................................................................................................... 79 14.0 Device Characterization - PIC16C54/55/56/57/CR54A.............................................................................................................. 91 15.0 Electrical Characteristics - PIC16C54A.................................................................................................................................... 103 16.0 Device Characterization - PIC16C54A ..................................................................................................................................... 117 17.0 Electrical Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ........................................ 131 18.0 Device Characterization - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B .......................................... 145 19.0 Electrical Characteristics - PIC16C54C/C55A/C56A/C57C/C58B 40MHz ............................................................................... 155 20.0 Device Characterization - PIC16C54C/C55A/C56A/C57C/C58B 40MHz ................................................................................ 165 21.0 Packaging Information.............................................................................................................................................................. 171 Appendix A: Compatibility ............................................................................................................................................................. 183 On-Line Support................................................................................................................................................................................. 189 Reader Response .............................................................................................................................................................................. 190 Product Identification System ............................................................................................................................................................ 191
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 3
PIC16C5X
NOTES:
DS30453D-page 4
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
8-Bit EPROM/ROM-Based CMOS Microcontrollers
1.0 GENERAL DESCRIPTION
1.1 Applications
The PIC16C5X from Microchip Technology is a family of low cost, high performance, 8-bit fully static, EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/ single cycle instructions. All instructions are single cycle except for program branches which take two cycles. The PIC16C5X delivers performance in an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C5X products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external RESET circuitry. There are four oscillator configurations to choose from, including the power saving LP (Low Power) oscillator and cost saving RC oscillator. Power saving SLEEP mode, Watchdog Timer and Code Protection features improve system cost, power and reliability. The UV erasable CERDIP packaged versions are ideal for code development, while the cost effective One Time Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP microcontrollers, while benefiting from the OTP's flexibility. The PIC16C5X products are supported by a full featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full featured programmer. All the tools are supported on IBM(R) PC and compatible machines. The PIC16C5X series fits perfectly in applications ranging from high speed automotive and appliance motor control to low power remote transmitters/receivers, pointing devices and telecom processors. The EPROM technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low cost, low power, high performance ease of use and I/O flexibility make the PIC16C5X series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of "glue" logic in larger systems, co-processor applications).
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 5
PIC16C5X
TABLE 1-1: PIC16C5X FAMILY OF DEVICES
Features Maximum Operation Frequency EPROM Program Memory (x12 words) ROM Program Memory (x12 words) RAM Data Memory (bytes) Timer Module(s) I/O Pins Number of Instructions Packages PIC16C54 40 MHz 512 -- 25 TMR0 12 33 PIC16CR54 20 MHz -- 512 25 TMR0 12 33 PIC16C55 40 MHz 512 -- 24 TMR0 20 33 PIC16C56 40 MHz 1K -- 25 TMR0 12 33 PIC16CR56 20 MHz -- 1K 25 TMR0 12 33
18-pin DIP, 18-pin DIP, 28-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 28-pin SSOP 20-pin SSOP 20-pin SSOP
All PICmicro(R) Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability.
Features Maximum Operation Frequency EPROM Program Memory (x12 words) ROM Program Memory (x12 words) RAM Data Memory (bytes) Timer Module(s) I/O Pins Number of Instructions Packages
PIC16C57 40 MHz 2K -- 72 TMR0 20 33
PIC16CR57 20 MHz -- 2K 72 TMR0 20 33
PIC16C58 40 MHz 2K -- 73 TMR0 12 33
PIC16CR58 20 MHz -- 2K 73 TMR0 12 33
28-pin DIP, SOIC; 28-pin DIP, SOIC; 18-pin DIP, SOIC; 18-pin DIP, SOIC; 28-pin SSOP 28-pin SSOP 20-pin SSOP 20-pin SSOP
All PICmicro(R) Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability.
DS30453D-page 6
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
2.0 PIC16C5X DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16C5X Product Identification System at the back of this data sheet to specify the correct part number. For the PIC16C5X family of devices, there are four device types, as indicated in the device number: 1. C, as in PIC16C54C. These devices have EPROM program memory and operate over the standard voltage range. LC, as in PIC16LC54A. These devices have EPROM program memory and operate over an extended voltage range. CR, as in PIC16CR54A. These devices have ROM program memory and operate over the standard voltage range. LCR, as in PIC16LCR54A. These devices have ROM program memory and operate over an extended voltage range.
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details.
2.4
2.
Serialized Quick-TurnaroundProduction (SQTPSM) Devices
3.
4.
Microchip offers the unique programming service where a few user defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number.
2.1
UV Erasable Devices (EPROM)
The UV erasable versions offered in CERDIP packages, are optimal for prototype development and pilot programs. UV erasable devices can be programmed for any of the four oscillator configurations. Microchip's PICSTART(R) Plus(1) and PRO MATE(R) programmers both support programming of the PIC16C5X. Third party programmers also are available. Refer to the Third Party Guide (DS00104) for a list of sources.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers expecting frequent code changes and updates, or small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must be programmed.
Note 1: PIC16C55A and PIC16C57C devices require OSC2 not to be connected while programming with PICSTART(R) Plus programmer.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 7
PIC16C5X
NOTES:
DS30453D-page 8
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C5X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C5X uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle except for program branches. The PIC16C54/CR54 and PIC16C55 address 512 x 12 of program memory, the PIC16C56/CR56 address 1K x 12 of program memory, and the PIC16C57/CR57 and PIC16C58/CR58 address 2K x 12 of program memory. All program memory is internal. The PIC16C5X can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC16C5X has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C5X simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16C5X device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1 (for PIC16C54/56/58) and Table 3-2 (for PIC16C55/ 57).
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 9
PIC16C5X
FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM
9-11 EPROM/ROM 512 X 12 TO 2048 X 12 12 INSTRUCTION REGISTER 9 12 8 INSTRUCTION DECODER DIRECT ADDRESS DIRECT RAM ADDRESS 6 OPTION REG. FROM W 5 8 LITERALS STATUS TMR0 DATA BUS ALU FROM W 4 "TRIS 5" TRISA PORTA 4 RA<3:0> 4 "TRIS 6" 8 FROM W 8 TRISB 8 PORTB "TRIS 7" FROM W 8 TRISC 8 FSR 8 W 5-7 "OPTION" GENERAL PURPOSE REGISTER FILE (SRAM) 24, 25, 72 or 73 Bytes WDT TIME OUT WDT/TMR0 PRESCALER CLKOUT 9-11 PC WATCHDOG TIMER "CODE PROTECT" STACK 1 STACK 2 T0CKI PIN OSC1 OSC2 MCLR
CONFIGURATION WORD "DISABLE"
"OSC SELECT" 2 OSCILLATOR/ TIMING & CONTROL
"SLEEP"
PORTC 8 RC<7:0> (28-Pin Devices Only)
8 RB<7:0>
DS30453D-page 10
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
TABLE 3-1:
Pin Name RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 T0CKI MCLR/VPP
PINOUT DESCRIPTION - PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, PIC16CR58
Pin Number Pin DIP SOIC SSOP Type 17 18 1 2 6 7 8 9 10 11 12 13 3 4 17 18 1 2 6 7 8 9 10 11 12 13 3 4 19 20 1 2 7 8 9 10 11 12 13 14 3 4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I Buffer Type TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL ST ST Bi-directional I/O port Description
Bi-directional I/O port
Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption.
Master clear (RESET) input/programming voltage input. This pin is an active low RESET to the device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode. OSC1/CLKIN 16 16 18 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 15 17 O -- Oscillator crystal output. Connects to crystal or resonator in crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. 14 14 15,16 P -- Positive supply for logic and I/O pins. VDD VSS 5 5 5,6 P -- Ground reference for logic and I/O pins. Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 11
PIC16C5X
TABLE 3-2:
Pin Name DIP RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 T0CKI MCLR 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 28 SOIC 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 28
PINOUT DESCRIPTION
Pin Number
- PIC16C55, PIC16C57, PIC16CR57
Description Bi-directional I/O port
Pin Buffer SSOP Type Type 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 2 28 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL ST ST
Bi-directional I/O port
Bi-directional I/O port
Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption.
Master clear (RESET) input. This pin is an active low RESET to the device. OSC1/CLKIN 27 27 27 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 26 26 26 O -- Oscillator crystal output. Connects to crystal or resonator in crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. 2 2 3,4 P -- Positive supply for logic and I/O pins. VDD VSS 4 4 1,14 P -- Ground reference for logic and I/O pins. N/C 3,5 3,5 -- -- -- Unused, do not connect. Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input
DS30453D-page 12
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 3-2 and Example 3-1.
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC
PC PC+1 PC+2
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Internal phase clock
OSC2/CLKOUT (RC mode)
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW H'55' 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 13
PIC16C5X
NOTES:
DS30453D-page 14
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
4.0
4.1
OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 4-2:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16C5X OSC2
PIC16C5Xs can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: 1. 2. 3. 4. LP: XT: HS: RC: Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor
Clock from ext. system Open
TABLE 4-1:
Note:
Not all oscillator selections available for all parts. See Section 9.1.
CAPACITOR SELECTION FOR CERAMIC RESONATORS PIC16C5X, PIC16CR5X
Cap. Range C1 Cap. Range C2
Osc Type XT
Resonator Freq
4.2
Crystal Oscillator/Ceramic Resonators
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 4-1). The PIC16C5X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 4-2).
455 kHz 68-100 pF 68-100 pF 2.0 MHz 15-33 pF 15-33 pF 4.0 MHz 10-22 pF 10-22 pF HS 8.0 MHz 10-22 pF 10-22 pF 16.0 MHz 10 pF 10 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
TABLE 4-2:
FIGURE 4-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR PIC16C5X, PIC16CR5X
Cap.Range C1 Cap. Range C2
Osc Type LP XT
Crystal Freq
C1(1)
PIC16C5X
SLEEP
XTAL OSC2 RS(2) C2(1)
RF(3)
To internal logic
Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the Oscillator mode chosen (approx. value = 10 M).
15 pF 15 pF 32 kHz(1) 100 kHz 15-30 pF 200-300 pF 200 kHz 15-30 pF 100-200 pF 455 kHz 15-30 pF 15-100 pF 1 MHz 15-30 pF 15-30 pF 2 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF HS 4 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF 20 MHz 15 pF 15 pF Note 1: For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
Note:
If you change from this device to another device, please verify oscillator characteristics in your application.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 15
PIC16C5X
4.3 External Crystal Oscillator Circuit
Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A welldesigned crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 4-3 shows an implementation example of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. Figure 4-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 4-4:
EXAMPLE OF EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)
330K 74AS04 74AS04 To Other Devices PIC16C5X CLKIN
330K 74AS04 0.1 F XTAL
Open
OSC2
FIGURE 4-3:
EXAMPLE OF EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)
To Other Devices
+5V 10K 4.7K 74AS04 Open 10K XTAL 10K 20 pF 20 pF 74AS04 PIC16C5X CLKIN OSC2
DS30453D-page 16
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
4.4 RC Oscillator
FIGURE 4-5:
VDD REXT OSC1 N Internal clock
RC OSCILLATOR MODE
For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 4-5 shows how the R/C combination is connected to the PIC16C5X. For REXT values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 3 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given REXT/ CEXT values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic.
CEXT VSS
PIC16C5X
OSC2/CLKOUT Fosc/4
Note:
If you change from this device to another device, please verify oscillator characteristics in your application.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 17
PIC16C5X
NOTES:
DS30453D-page 18
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
5.0 RESET
PIC16C5X devices may be RESET in one of the following ways: * * * * * Power-On Reset (POR) MCLR Reset (normal operation) MCLR Wake-up Reset (from SLEEP) WDT Reset (normal operation) WDT Wake-up Reset (from SLEEP) The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different RESET conditions (Table 51). These bits may be used to determine the nature of the RESET. Table 5-3 lists a full description of RESET states of all registers. Figure 5-1 shows a simplified block diagram of the On-chip Reset circuit.
Table 5-1 shows these RESET conditions for the PCL and STATUS registers. Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on Power-On Reset (POR), MCLR or WDT Reset. A MCLR or WDT wake-up from SLEEP also results in a device RESET, and not a continuation of operation before SLEEP.
TABLE 5-1:
Power-On Reset
STATUS BITS AND THEIR SIGNIFICANCE
Condition TO 1 u 1 0 0 PD 1 u 0 1 0
MCLR Reset (normal operation) MCLR Wake-up (from SLEEP) WDT Reset (normal operation) WDT Wake-up (from SLEEP) Legend: u = unchanged, x = unknown, -- = unimplemented read as '0'.
TABLE 5-2:
Address 03h Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESET
Bit 7 PA2 Bit 6 PA1 Bit 5 PA0 Bit 4 TO Bit 3 PD Bit 2 Z Bit 1 DC Bit 0 C Value on POR 0001 1xxx Value on MCLR and WDT Reset 000q quuu
STATUS
Legend:
u = unchanged, x = unknown, q = see Table 5-1 for possible values.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 19
PIC16C5X
TABLE 5-3: RESET CONDITIONS FOR ALL REGISTERS
Register Address Power-On Reset MCLR or WDT Reset uuuu 1111 --11 uuuu uuuu 1111 000q 1uuu ---uuuu uuuu uuuu uuuu 1111 1111 uuuu uuuu 1111 quuu uuuu uuuu uuuu uuuu uuuu
W N/A xxxx xxxx TRIS N/A 1111 1111 OPTION N/A --11 1111 INDF 00h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h 1111 1111 STATUS 03h 0001 1xxx FSR(1) 04h 1xxx xxxx PORTA 05h ---- xxxx PORTB 06h xxxx xxxx PORTC(2) 07h xxxx xxxx General Purpose Register Files 07-7Fh xxxx xxxx Legend: x = unknown u = unchanged - = unimplemented, read as '0' q = see tables in Table 5-1 for possible values.
Note 1: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu. 2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up Detect VDD POR (Power-On Reset)
MCLR/VPP pin
WDT Time-out RESET WDT On-Chip RC OSC 8-bit Asynch Ripple Counter (Device Reset Timer) S Q
R
Q CHIP RESET
DS30453D-page 20
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
5.1 Power-On Reset (POR)
FIGURE 5-2:
The PIC16C5X family incorporates on-chip Power-On Reset (POR) circuitry which provides an internal chip RESET for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 5-1. The Power-On Reset circuit and the Device Reset Timer (Section 5.2) circuit are closely related. On power-up, the RESET latch is set and the DRT is RESET. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will RESET the reset latch and thus end the on-chip RESET signal. A power-up example where MCLR is not tied to VDD is shown in Figure 5-3. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. In Figure 5-4, the on-chip Power-On Reset feature is being used (MCLR and VDD are tied together). The VDD is stable before the start-up timer times out and there is no problem in getting a proper RESET. However, Figure 5-5 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses a high on the MCLR/VPP pin, and when the MCLR/VPP pin (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 5-2). Note: When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
VDD
D
R R1 MCLR C PIC16C5X
* External Power-On Reset circuit is required only if VDD power-up is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. * R < 40 k is recommended to make sure that voltage drop across R does not violate the device electrical specification. * R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
For more information on PIC16C5X POR, see PowerUp Considerations - AN522 in the Embedded Control Handbook. The POR circuit does not produce an internal RESET when VDD declines.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 21
PIC16C5X
FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT INTERNAL RESET
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1 VDD MCLR
INTERNAL POR TDRT
DRT TIME-OUT
INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will RESET properly if, and only if, V1 VDD min
DS30453D-page 22
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
5.2 Device Reset Timer (DRT)
FIGURE 5-7:
VDD VDD R1 Q1 MCLR R2 40K PIC16C5X
The Device Reset Timer (DRT) provides an 18 ms nominal time-out on RESET regardless of Oscillator mode used. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after the voltage on the MCLR/VPP pin has reached a logic high (VIH) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications. The Device Reset time delay will vary from chip to chip due to VDD, temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the PIC16C5X from SLEEP mode automatically.
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD * R1 R1 + R2 = 0.7V
FIGURE 5-8:
VDD
VDD MCP809 RST Vss
5.3
Reset on Brown-Out
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3
A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be RESET in the event of a brown-out. To RESET PIC16C5X devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 5-6, Figure 5-7 and Figure 58.
bypass capacitor
VDD
MCLR
PIC16C5X
FIGURE 5-6:
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD VDD 33K 10K Q1 MCLR 40K PIC16C5X
This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both "active high and active low" RESET pins. There are 7 different trip point selections to accommodate 5V and 3V systems.
This circuit will activate RESET when VDD goes below Vz + 0.7V (where Vz = Zener voltage).
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 23
PIC16C5X
NOTES:
DS30453D-page 24
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
6.0 MEMORY ORGANIZATION
FIGURE 6-2:
PIC16C5X memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS Register bits. For devices with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR).
PIC16C56/CR56 PROGRAM MEMORY MAP AND STACK
PC<9:0> 10 Stack Level 1 Stack Level 2
000h
CALL, RETLW
The PIC16C54, PIC16CR54 and PIC16C55 have a 9bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 6-1). The PIC16C56 and PIC16CR56 have a 10-bit Program Counter (PC) capable of addressing a 1K x 12 program memory space (Figure 6-2). The PIC16CR57, PIC16C58 and PIC16CR58 have an 11-bit Program Counter capable of addressing a 2K x 12 program memory space (Figure 6-3). Accessing a location above the physically implemented address will cause a wraparound. A NOP at the RESET vector location will cause a restart at location 000h. The RESET vector for the PIC16C54, PIC16CR54 and PIC16C55 is at 1FFh. The RESET vector for the PIC16C56 and PIC16CR56 is at 3FFh. The RESET vector for the PIC16C57, PIC16CR57, PIC16C58, and PIC16CR58 is at 7FFh. See Section 6.5 for additional information using CALL and GOTO instructions.
User Memory Space
6.1
Program Memory Organization
On-chip Program Memory (Page 0)
0FFh 100h 1FFh 200h
On-chip Program Memory (Page 1) RESET Vector
2FFh 300h
3FFh
FIGURE 6-3:
PIC16C57/CR57/C58/ CR58 PROGRAM MEMORY MAP AND STACK
PC<10:0> 11 Stack Level 1 Stack Level 2
000h
CALL, RETLW
FIGURE 6-1:
PIC16C54/CR54/C55 PROGRAM MEMORY MAP AND STACK
PC<8:0> 9 Stack Level 1 Stack Level 2
000h
On-chip Program Memory (Page 0)
0FFh 100h 1FFh 200h
User Memory Space
CALL, RETLW
On-chip Program Memory (Page 1)
2FFh 300h 3FFh 400h
On-chip Program Memory (Page 2)
User Memory Space
4FFh 500h 5FFh 600h
On-chip Program Memory
0FFh 100h
On-chip Program Memory (Page 3) RESET Vector
6FFh 700h 7FFh
RESET Vector
1FFh
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 25
PIC16C5X
6.2 Data Memory Organization
FIGURE 6-4:
Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers and General Purpose Registers. The Special Function Registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports) and the File Select Register (FSR). In addition, Special Purpose Registers are used to control the I/O port configuration and prescaler options. The General Purpose Registers are used for data and control information under command of the instructions. For the PIC16C54, PIC16CR54, PIC16C56 and PIC16CR56, the register file is composed of 7 Special Function Registers and 25 General Purpose Registers (Figure 6-4). For the PIC16C55, the register file is composed of 8 Special Function Registers and 24 General Purpose Registers. For the PIC16C57 and PIC16CR57, the register file is composed of 8 Special Function Registers, 24 General Purpose Registers and up to 48 additional General Purpose Registers that may be addressed using a banking scheme (Figure 6-5). For the PIC16C58 and PIC16CR58, the register file is composed of 7 Special Function Registers, 25 General Purpose Registers and up to 48 additional General Purpose Registers that may be addressed using a banking scheme (Figure 6-6).
1Fh
PIC16C54, PIC16CR54, PIC16C55, PIC16C56, PIC16CR56 REGISTER FILE MAP
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h General Purpose Registers INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC(2)
Note 1: Not a physical register. See Section 6.7. 2: PIC16C55 only, in all other devices this is implemented as a a general purpose register.
6.2.1
GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly or indirectly through the File Select Register (FSR). The FSR Register is described in Section 6.7.
DS30453D-page 26
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 6-5: PIC16C57/CR57 REGISTER FILE MAP
00 INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC General Purpose Registers General Purpose Registers 1Fh Bank 0 3Fh Bank 1 Addresses map back to addresses in Bank 0. 20h 01 40h 10 60h 11 FSR<6:5> File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Fh 10h
2Fh 30h General Purpose Registers
4Fh 50h General Purpose Registers 5Fh Bank 2
6Fh 70h General Purpose Registers 7Fh Bank 3
Note 1: Not a physical register. See Section 6.7.
FIGURE 6-6:
PIC16C58/CR58 REGISTER FILE MAP
00 INDF(1) TMR0 PCL STATUS FSR PORTA PORTB General Purpose Registers 0Fh 10h General Purpose Registers 1Fh Bank 0 3Fh Bank 1 2Fh 30h General Purpose Registers 5Fh Bank 2 4Fh 50h General Purpose Registers 7Fh Bank 3 6Fh 70h General Purpose Registers Addresses map back to addresses in Bank 0. 20h 01 40h 10 60h 11
FSR<6:5> File Address 00h 01h 02h 03h 04h 05h 06h 07h
Note 1: Not a physical register. See Section 6.7.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 27
PIC16C5X
6.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device (Table 6-1). The Special Registers can be classified into two sets. The Special Function Registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
TABLE 6-1:
Address
N/A N/A 00h 01h 02h 03h 04h 05h 06h 07h(2)
(1)
SPECIAL FUNCTION REGISTER SUMMARY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset 1111 1111 --11 1111 xxxx xxxx xxxx xxxx 1111 1111
TO -- RB4 RC4 PD RA3 RB3 RC3 Z RA2 RB2 RC2 DC RA1 RB1 RC1 C RA0 RB0 RC0
Details on Page
35 30 32 38 31 29 32 35 35 35
TRIS OPTION INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC
I/O Control Registers (TRISA, TRISB, TRISC) Contains control bits to configure Timer0 and Timer0/WDT prescaler Uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Low order 8 bits of PC PA2 -- RB7 RC7 PA1 -- RB6 RC6 PA0 -- RB5 RC5
0001 1xxx 1xxx xxxx(3) ---- xxxx xxxx xxxx xxxx xxxx
Indirect data memory address pointer
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused Note 1: The upper byte of the Program Counter is not directly accessible. See Section 6.5 for an explanation of how to access these bits. 2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and PIC16CR58. 3: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu.
DS30453D-page 28
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
6.3 STATUS Register
This register contains the arithmetic status of the ALU, the RESET status and the page preselect bits for program memories larger than 512 words. The STATUS Register can be the destination for any instruction, as with any other register. If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS Register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS Register because these instructions do not affect the Z, DC or C bits from the STATUS Register. For other instructions which do affect STATUS Bits, see Section 10.0, Instruction Set Summary.
REGISTER 6-1:
R/W-0 PA2 bit 7 bit 7:
STATUS REGISTER (ADDRESS: 03h)
R/W-0 PA1 R/W-0 PA0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
PA2: This bit unused at this time. Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. PA<1:0>: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(PIC16C58/CR58) 00 = Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58 01 = Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58 10 = Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58 11 = Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58 Each page is 512 words. Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended since this may affect upward compatibility with future products. TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Loaded with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred
bit 6-5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 29
PIC16C5X
6.4 OPTION Register
The OPTION Register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W Register will be transferred to the OPTION Register. A RESET sets the OPTION<5:0> bits.
REGISTER 6-2:
U-0 -- bit 7 bit 7-6: bit 5:
OPTION REGISTER
U-0 -- W-1 T0CS W-1 TOSE W-1 PSA W-1 PS2 W-1 PS1 W-1 PS0 bit 0
Unimplemented: Read as `0' T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 source edge select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 PS<2:0>: Prescaler rate select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 4:
bit 3:
bit 2-0:
Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
DS30453D-page 30
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
6.5 Program Counter
FIGURE 6-8:
As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure 6-7, Figure 6-8 and Figure 6-9). For the PIC16C56, PIC16CR56, PIC16C57, PIC16CR57, PIC16C58 and PIC16CR58, a page number must be supplied as well. Bit5 and bit6 of the STATUS Register provide page information to bit9 and bit10 of the PC (Figure 6-8 and Figure 6-9). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 6-7 and Figure 6-8). Instructions where the PCL is the destination, or modify PCL instructions, include MOVWF PCL, ADDWF PCL, and BSF PCL,5. For the PIC16C56, PIC16CR56, PIC16C57, PIC16CR57, PIC16C58 and PIC16CR58, a page number again must be supplied. Bit5 and bit6 of the STATUS Register provide page information to bit9 and bit10 of the PC (Figure 6-8 and Figure 6-9). Note: Because PC<8> is cleared in the CALL instruction, or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).
7 0 STATUS
LOADING OF PC BRANCH INSTRUCTIONS - PIC16C56/PIC16CR56
GOTO Instruction
PC 10 0 9 87 PCL 0
Instruction Word 2 PA<1:0> 0
CALL or Modify PCL Instruction
10 PC 0 9 87 PCL 0
Instruction Word Reset to `0' PA<1:0> 0 0 STATUS
2 7
FIGURE 6-9:
LOADING OF PC BRANCH INSTRUCTIONS - PIC16C57/PIC16CR57, AND PIC16C58/ PIC16CR58
9 87 PCL 0
GOTO Instruction
10 PC
FIGURE 6-7:
LOADING OF PC BRANCH INSTRUCTIONS - PIC16C54, PIC16CR54, PIC16C55
Instruction Word 2 7 PA<1:0> 0
GOTO Instruction
8 PC 7 PCL 0
STATUS
Instruction Word
CALL or Modify PCL Instruction
10 9 87 PCL 0 PC
CALL or Modify PCL Instruction
8 PC 7 PCL 0
Instruction Word Reset to `0' PA<1:0> 0
Reset to '0'
Instruction Word 7
2
STATUS
(c) 2002 Microchip Technology Inc.
Preliminary
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PIC16C5X
6.5.1 PAGING CONSIDERATIONS - PIC16C56/CR56, PIC16C57/CR57 AND PIC16C58/CR58
If the Program Counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. However, the page preselect bits in the STATUS Register will not be updated. Therefore, the next GOTO, CALL or modify PCL instruction will send the program to the page specified by the page preselect bits (PA0 or PA<1:0>). For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address xxh on page 0 (assuming that PA<1:0> are clear). To prevent this, the page preselect bits must be updated under program control.
6.5.2
EFFECTS OF RESET
The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page (i.e., the RESET vector). The STATUS Register page preselect bits are cleared upon a RESET, which means that page 0 is preselected. Therefore, upon a RESET, a GOTO instruction at the RESET vector location will automatically cause the program to jump to page 0.
6.6
Stack
PIC16C5X devices have a 10-bit or 11-bit wide, twolevel hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL's are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW's are executed, the stack will be filled with the address previously stored in level 2. Note that the W Register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. For the RETLW instruction, the PC is loaded with the Top of Stack (TOS) contents. All of the devices covered in this data sheet have a two-level stack. The stack has the same bit width as the device PC, therefore, paging is not an issue when returning from a subroutine.
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Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
6.7 Indirect Data Addressing; INDF and FSR Registers
EXAMPLE 6-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
H'10' FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF Register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF Register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR Register (FSR is a pointer). This is indirect addressing.
NEXT
EXAMPLE 6-1:
* * * *
INDIRECT ADDRESSING
CONTINUE
MOVLW MOVWF CLRF INCF BTFSC GOTO :
Register file 08 contains the value 10h Register file 09 contains the value 0Ah Load the value 08 into the FSR Register A read of the INDF Register will return the value of 10h * Increment the value of the FSR Register by one (FSR = 09h) * A read of the INDF register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF Register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 6-2.
The FSR is either a 5-bit (PIC16C54, PIC16CR54, PIC16C55, PIC16C56, PIC16CR56) or 7-bit (PIC16C57, PIC16CR57, PIC16C58, PIC16CR58) wide register. It is used in conjunction with the INDF Register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC16C54, PIC16CR54, PIC16C55, PIC16C56, PIC16CR56: These do not use banking. FSR<6:5> bits are unimplemented and read as '1's. PIC16C57, PIC16CR57, PIC16C58, PIC16CR58: FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = bank 0, 01 = bank 1, 10 = bank 2, 11 = bank 3).
FIGURE 6-10:
(FSR) 6 5
DIRECT/INDIRECT ADDRESSING
Indirect Addressing (FSR) 0 6 5 4 3 2 1 0
Direct Addressing (opcode) 4 3 2 1
bank select
location select 00 00h Addresses map back to addresses in Bank 0. Data Memory(1) 0Fh 10h 01 10 11
bank
location select
1Fh Bank 0
3Fh Bank 1
5Fh Bank 2
7Fh Bank 3
Note 1: For register map detail see Section 6.2.
(c) 2002 Microchip Technology Inc.
Preliminary
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PIC16C5X
NOTES:
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Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
7.0 I/O PORTS
7.5 I/O Interfacing
As with any other register, the I/O Registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin's input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers (TRISA, TRISB, TRISC) are all set. The equivalent circuit for an I/O port pin is shown in Figure 7-1. All ports may be used for both input and output operation. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB, TRISC) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output.
7.1
PORTA
PORTA is a 4-bit I/O Register. Only the low order 4 bits are used (RA<3:0>). Bits 7-4 are unimplemented and read as '0's.
7.2
PORTB
FIGURE 7-1:
Data Bus D WR Port Data Latch CK
PORTB is an 8-bit I/O Register (PORTB<7:0>).
EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
Q VDD Q P
7.3
PORTC
PORTC is an 8-bit I/O Register for PIC16C55, PIC16C57 and PIC16CR57. PORTC is a General Purpose Register for PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and PIC16CR58.
7.4
TRIS Registers
W Reg
N D TRIS Latch Q VSS Q
I/O pin(1)
The Output Driver Control Registers are loaded with the contents of the W Register by executing the TRIS f instruction. A '1' from a TRIS Register bit puts the corresponding output driver in a hi-impedance (input) mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.
TRIS `f'
CK
RESET
RD Port Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS Registers are "write-only" and are set (output drivers disabled) upon RESET.
TABLE 7-1:
Address N/A 05h 06h 07h
SUMMARY OF PORT REGISTERS
Name TRIS PORTA PORTB PORTC -- RB7 RC7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset 1111 1111 RA0 RB0 RC0 ---- xxxx xxxx xxxx xxxx xxxx Value on MCLR and WDT Reset 1111 1111 ---- uuuu uuuu uuuu uuuu uuuu
I/O Control Registers (TRISA, TRISB, TRISC) -- RB6 RC6 -- RB5 RC5 -- RB4 RC4 RA3 RB3 RC3 RA2 RB2 RC2 RA1 RB1 RC1
Legend: x = unknown, u = unchanged, -- = unimplemented, read as '0', Shaded cells = unimplemented, read as `0'
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 35
PIC16C5X
7.6
7.6.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 7-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit0 is switched into Output mode later on, the content of the data latch may now be unknown. Example 7-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.
;Initial PORT Settings ; PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- ---------BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp MOVLW H'3F' ; TRIS PORTB ;10pp pppp 10pp pppp ; ;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High).
7.6.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 72). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
FIGURE 7-2:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 MOVF PORTB,W PC + 2 NOP Q1 Q2 Q3 Q4 PC + 3 NOP
Instruction fetched RB<7:0>
MOVWF PORTB
Port pin written here
Port pin sampled here
This example shows a write to PORTB followed by a read from PORTB.
Instruction executed
MOVWF PORTB (Write to PORTB)
MOVF PORTB,W (Read PORTB)
NOP
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Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
8.0 TIMER0 MODULE AND TMR0 REGISTER
Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 8.1. Note: The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both.
The Timer0 module has the following features: * 8-bit timer/counter register, TMR0 - Readable and writable * 8-bit software programmable prescaler * Internal or external clock select - Edge select for external clock Figure 8-1 is a simplified block diagram of the Timer0 module, while Figure 8-2 shows the electrical structure of the Timer0 input. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 8-3 and Figure 8-4). The user can work around this by writing an adjusted value to the TMR0 register.
The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 8.2 details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 8-1.
FIGURE 8-1:
TIMER0 BLOCK DIAGRAM
Data Bus FOSC/4 0 1 1 PSout Sync with Internal Clocks 8 TMR0 reg
T0CKI pin
T0SE(1)
Programmable Prescaler(2) 3 T0CS(1) PS2, PS1, PS0(1)
0
PSout (2 cycle delay) Sync
PSA(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register (Section 6.4). 2: The prescaler is shared with the Watchdog Timer (Figure 8-6).
FIGURE 8-2:
ELECTRICAL STRUCTURE OF T0CKI PIN
RIN T0CKI pin
(1)
N
(1)
Schmitt Trigger Input Buffer
VSS
VSS
Note 1: ESD protection circuits.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 37
PIC16C5X
FIGURE 8-3:
PC (Program Counter) Instruction Fetch
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 PC+2 PC+3 PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Timer0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
FIGURE 8-4:
PC (Program Counter) Instruction Fetch Timer0 T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 PC+2 PC+3 PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
T0
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
TABLE 8-1:
Address 01h N/A
REGISTERS ASSOCIATED WITH TIMER0
Name TMR0 OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset xxxx xxxx PSA PS2 PS1 PS0 --11 1111 Value on MCLR and WDT Reset uuuu uuuu --11 1111
Timer0 - 8-bit real-time clock/counter -- -- T0CS T0SE
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells not used by Timer0.
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Preliminary
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PIC16C5X
8.1 Using Timer0 with an External Clock
When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.
8.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 8-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
8.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 8-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 8-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler Output (1) (3) External Clock/Prescaler Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (2)
T0 + 2
Note 1: External clock if no prescaler selected, prescaler output otherwise. 2: The arrows indicate the points in time where sampling occurs. 3: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc (duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 39
PIC16C5X
8.2 Prescaler
EXAMPLE 8-1:
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 9.2.1). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's.
CHANGING PRESCALER (TIMER0WDT)
;Clear WDT ;Clear TMR0 & Prescaler ;Last 3 instructions in this example OPTION ;are required only if ;desired CLRWDT ;PS<2:0> are 000 or ;001 MOVLW B'00xx1xxx' ;Set Prescaler to OPTION ;desired WDT rate
CLRWDT CLRF TMR0 MOVLW B'00xx1111'
To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 8-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.
EXAMPLE 8-2:
CLRWDT MOVLW B'xxxx0xxx'
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source
8.2.1
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 8-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.
OPTION
DS30453D-page 40
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 8-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 T0CKI pin 1 M U X 1 0 T0SE T0CS PSA M U X Sync 2 Cycles TMR0 reg 8 TCY ( = FOSC/4)
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS<2:0>
Watchdog Timer
1
PSA WDT Enable bit 0 MUX 1 PSA
WDT Time-Out Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 41
PIC16C5X
NOTES:
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Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
9.0 SPECIAL FEATURES OF THE CPU
What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC16C5X family of microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: * * * * * * * * Oscillator Selection (Section 4.0) RESET (Section 5.0) Power-On Reset (Section 5.1) Device Reset Timer (Section 5.2) Watchdog Timer (WDT) (Section 9.2) SLEEP (Section 9.3) Code protection (Section 9.4) ID locations (Section 9.5)
The PIC16C5X Family has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in RESET until the crystal oscillator is stable. With this timer on-chip, most applications need no external RESET circuitry. The SLEEP mode is designed to offer a very low current Power-down mode. The user can wake up from SLEEP through external RESET or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 43
PIC16C5X
9.1 Configuration Bits
Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type and one bit is the Watchdog Timer enable bit. Nine bits are code protection bits for the PIC16C54A, PIC16CR54A, PIC16C54C, PIC16CR54C, PIC16C55A, PIC16C56A, PIC16CR56A, PIC16C57C, PIC16CR57C, PIC16C58B, and PIC16CR58B devices (Register 9-1). One bit is for code protection for the PIC16C54, PIC16C55, PIC16C56 and PIC16C57 devices (Register 9-2). QTP or ROM devices have the oscillator configuration programmed at the factory and these parts are tested accordingly (see "Product Identification System" diagrams in the back of this data sheet).
REGISTER 9-1:
CONFIGURATION WORD FOR PIC16C54A/CR54A/C54C/CR54C/C55A/C56A/ CR56A/C57C/CR57C/C58B/CR58B
CP CP CP CP CP CP CP WDTE FOSC1 FOSC0
CP
CP
bit 11 bit 11-3: CP: Code Protection Bit 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection Bit 00 = LP oscillator 01 = XT oscillator 10 = HS oscillator 11 = RC oscillator
bit 0
bit 1-0:
Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to access the configuration word. Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
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Preliminary
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PIC16C5X
REGISTER 9-2:
-- --
CONFIGURATION WORD FOR PIC16C54/C55/C56/C57
-- -- -- -- -- -- CP WDTE FOSC1 FOSC0
bit 11 bit 11-4: Unimplemented: Read as `0' bit 3: CP: Code protection bit. 1 = Code protection off 0 = Code protection on WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator selection bits(2) 00 = LP oscillator 01 = XT oscillator 10 = HS oscillator 11 = RC oscillator
bit 0
bit 2:
bit 1-0:
Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the configuration word. 2: PIC16LV54A supports XT, RC and LP oscillator only. Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
(c) 2002 Microchip Technology Inc.
Preliminary
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PIC16C5X
9.2 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT Reset or Wake-up Reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset (Section 6.3). The WDT can be permanently disabled by programming the configuration bit WDTE as a '0' (Section 9.1). Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the configuration word. both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio (Section 6.4). The WDT has a nominal time-out period of 18 ms (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, time-out a period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see Device Characterization). Under worst case conditions (VDD = Min., Temperature = Max., WDT prescaler = 1:128), it may take several seconds before a WDT time-out occurs.
9.2.2
9.2.1
WDT PERIOD
WDT PROGRAMMING CONSIDERATIONS
An 8-bit counter is available as a prescaler for the Timer0 module (Section 8.2), or as a postscaler for the Watchdog Timer (WDT), respectively. For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not
The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction RESETS the WDT and the prescaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT Wake-up Reset.
FIGURE 9-1:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Watchdog Timer 1 M U X 8 - to - 1 MUX WDT Enable EPROM Bit To TMR0 0 MUX 1 PSA PSA PS2:PS0 Prescaler
Note:
T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
WDT Time-out
TABLE 9-1:
Address N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name OPTION Bit 7 -- Bit 6 -- Bit 5 Tosc Bit 4 Tose Bit 3 PSA Bit 2 PS2 Bit 1 PS1 Bit 0 PS0 Value on Value on Power-On MCLR and Reset WDT Reset --11 1111 --11 1111
Legend: u = unchanged, - = unimplemented, read as '0'. Shaded cells not used by Watchdog Timer.
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9.3 Power-Down Mode (SLEEP) 9.4
A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP).
Program Verification/Code Protection
9.3.1
SLEEP
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR/VPP pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the MCLR/VPP pin must be at a logic high level (MCLR = VIH).
9.5
ID Locations
Four memory locations are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as '1's. Note: Microchip will assign a unique pattern number for QTP and SQTP requests and for ROM devices. This pattern number will be unique and traceable to the submitted code.
9.3.2
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of the following events: 1. 2. An external RESET input on MCLR/VPP pin. A Watchdog Timer Time-out Reset (if WDT was enabled).
Both of these events cause a device RESET. The TO and PD bits can be used to determine the cause of device RESET. The TO bit is cleared if a WDT timeout occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The WDT is cleared when the device wakes from SLEEP, regardless of the wake-up source.
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NOTES:
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10.0 INSTRUCTION SET SUMMARY
Each PIC16C5X instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C5X instruction set summary in Table 10-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 10-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator is used to specify which one of the 32 file registers in that bank is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time would be 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time would be 2 s. Figure 10-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where 'h' signifies a hexadecimal digit.
FIGURE 10-1:
GENERAL FORMAT FOR INSTRUCTIONS
6 5 d 4 f (FILE #) 0
Byte-oriented file register operations 11 OPCODE
TABLE 10-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 87 54 b (BIT #) f (FILE #) 0
Register file address (0x00 to 0x1F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0 (store result in W) d = 1 (store result in file register 'f') Default is d = 1 label Label name TOS Top of Stack PC Program Counter WDT Watchdog Timer Counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [] Options () Contents Assigned to <> Register bit field In the set of italics User defined term (font is courier)
b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 OPCODE k = 8-bit immediate value Literal and control operations - GOTO instruction 11 OPCODE k = 9-bit immediate value 9 8 k (literal) 0 8 7 k (literal) 0
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TABLE 10-2:
Mnemonic, Operands
INSTRUCTION SET SUMMARY
12-Bit Opcode Description Cycles MSb LSb Status Notes Affected
0001 11df ffff C,DC,Z ADDWF f,d Add W and f 1 1,2,4 0001 01df ffff ANDWF f,d AND W with f Z 1 2,4 0000 011f ffff CLRF f Clear f Z 1 4 0000 0100 0000 CLRW - Clear W Z 1 0010 01df ffff COMF f, d Complement f Z 1 0000 11df ffff DECF f, d Decrement f Z 1 2,4 0010 11df ffff DECFSZ f, d Decrement f, Skip if 0 None 1(2) 2,4 1 0010 10df ffff INCF f, d Increment f Z 2,4 1(2) 0011 11df ffff INCFSZ f, d Increment f, Skip if 0 None 2,4 1 0001 00df ffff IORWF f, d Inclusive OR W with f Z 2,4 1 0010 00df ffff MOVF f, d Move f Z 2,4 1 0000 001f ffff MOVWF f Move W to f None 1,4 1 0000 0000 0000 NOP - No Operation None 1 0011 01df ffff RLF f, d Rotate left f through Carry C 2,4 1 0011 00df ffff RRF f, d Rotate right f through Carry C 2,4 1 0000 10df ffff C,DC,Z SUBWF f, d Subtract W from f 1,2,4 1 0011 10df ffff SWAPF f, d Swap f None 2,4 1 0001 10df ffff XORWF f, d Exclusive OR W with f Z 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS 0100 bbbf ffff None 2,4 BCF f, b Bit Clear f 1 0101 bbbf ffff None 2,4 BSF f, b Bit Set f 1 0110 bbbf ffff None f, b Bit Test f, Skip if Clear 1 (2) BTFSC 1 (2) 0111 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL 1 k Call subroutine 2 1001 kkkk kkkk None CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TO, PD None GOTO k Unconditional branch 2 101k kkkk kkkk Z IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk None MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION k Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk SLEEP - Go into standby mode 1 0000 0000 0011 TO, PD None 3 TRIS f Load TRIS register 1 0000 0000 0fff Z XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO (see Section 6.5 for more on program counter). 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instruction TRIS f, where f = 5, 6 or 7 causes the contents of the W register to be written to the tristate latches of PORTA, B or C respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).
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ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Add W and f [ label ] ADDWF 0 f 31 d [0,1] (W) + (f) (dest) C, DC, Z 0001 11df ffff Add the contents of the W register and register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. 1 1 ADDWF TEMP_REG, 0 0x17 0xC2 0xD9 0xC2 f,d ANDWF Syntax: Operands: Operation: Status Affected: Encoding: Description: AND W with f [ label ] ANDWF 0 f 31 d [0,1] (W) .AND. (f) (dest) Z 0001 01df ffff The contents of the W register are AND'ed with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. 1 1 ANDWF TEMP_REG, 1 0x17 0xC2 0x17 0x02 f,d
Words: Cycles: Example:
Words: Cycles: Example:
Before Instruction W = TEMP_REG = After Instruction W = TEMP_REG =
Before Instruction W = TEMP_REG = After Instruction W = TEMP_REG =
ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W).AND. (k) (W) Z 1110 kkkk kkkk The contents of the W register are AND'ed with the eight-bit literal 'k'. The result is placed in the W register. 1 1 ANDLW H'5F' k
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example:
Bit Clear f [ label ] BCF 0 f 31 0b7 0 (f) None 0100 1 1 BCF FLAG_REG, 0xC7 0x47 7 bbbf ffff Bit 'b' in register 'f' is cleared. f,b
Words: Cycles: Example:
Before Instruction W = 0xA3 After Instruction W = 0x03
Before Instruction FLAG_REG = After Instruction FLAG_REG =
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BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example: Bit Set f [ label ] BSF 0 f 31 0b7 1 (f) None 0101 1 1 BSF FLAG_REG, 7 bbbf ffff Bit 'b' in register 'f' is set. f,b BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 31 0b<7 skip if (f) = 1 None 0111 bbbf ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2-cycle instruction. 1 1(2) HERE FALSE TRUE BTFSS FLAG,1 GOTO PROCESS_CODE * * * = = = = = address (HERE) 0, address (FALSE); 1, address (TRUE)
Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A
Words: Cycles: Example:
BTFSC Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 31 0b7 skip if (f) = 0 None 0110 bbbf ffff If bit 'b' in register 'f' is 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2-cycle instruction. 1 1(2) HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE * * * = address (HERE) = = = = 0, address (TRUE); 1, address(FALSE)
Before Instruction PC After Instruction If FLAG<1> PC if FLAG<1> PC
Words: Cycles: Example:
Before Instruction PC After Instruction if FLAG<1> PC if FLAG<1> PC
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CALL Syntax: Operands: Operation: Subroutine Call [ label ] CALL k 0 k 255 (PC) + 1 TOS; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8> None 1001 kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a twocycle instruction. 1 2 HERE CALL THERE CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD TO, PD 0000 0000 0100 The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. 1 1 CLRWDT = = = = = ? 0x00 0 1 1 CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example: Clear W [ label ] CLRW None 00h (W); 1Z Z 0000 0100 0000 The W register is cleared. Zero bit (Z) is set. 1 1 CLRW
Status Affected: Encoding: Description:
Words: Cycles: Example:
Before Instruction W = 0x5A After Instruction W = 0x00 Z =1
Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 1)
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example:
Clear f [ label ] CLRF 0 f 31 00h (f); 1Z Z 0000 011f ffff The contents of register 'f' are cleared and the Z bit is set. 1 1 CLRF FLAG_REG 0x5A 0x00 1 f
Status Affected: Encoding: Description:
Words: Cycles: Example:
Before Instruction FLAG_REG = After Instruction FLAG_REG = Z =
Before Instruction WDT counter After Instruction WDT counter WDT prescaler TO PD
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COMF Syntax: Operands: Operation: Status Affected: Encoding: Description: Complement f [ label ] COMF 0 f 31 d [0,1] (f) (dest) Z 0010 01df ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 COMF REG1,0 0x13 0x13 0xEC Words: Cycles: Example: f,d DECFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 31 d [0,1] (f) - 1 d; None 0010 11df ffff The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. 1 1(2) HERE DECFSZ GOTO CONTINUE * * * address(HERE) CNT - 1; 0, address (CONTINUE); 0, address (HERE+1) CNT, 1 LOOP skip if result = 0
Words: Cycles: Example:
Before Instruction REG1 = After Instruction REG1 = W =
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 31 d [0,1] (f) - 1 (dest) Z 0000 11df ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 DECF CNT, 1 0x01 0 0x00 1
Before Instruction PC = After Instruction CNT = if CNT = PC = if CNT PC =
Words: Cycles: Example:
Before Instruction CNT = Z = After Instruction CNT = Z =
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GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 511 k PC<8:0>; STATUS<6:5> PC<10:9> None 101k kkkk kkkk GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a twocycle instruction. 1 2 GOTO THERE Words: Cycles: Example: INCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f [ label ] 0 f 31 d [0,1] (f) + 1 (dest) Z 0010 10df ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. 1 1 INCF CNT, 1 INCF f,d INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] 0 f 31 d [0,1] (f) + 1 (dest), skip if result = 0 None 0011 11df ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a twocycle instruction. 1 1(2) INCFSZ GOTO CONTINUE * * * address (HERE) CNT + 1; 0, address (CONTINUE); 0, address (HERE +1) HERE CNT, 1 LOOP INCFSZ f,d
Words: Cycles: Example:
After Instruction PC = address (THERE)
Before Instruction PC = After Instruction CNT = if CNT = PC = if CNT PC =
Words: Cycles: Example:
Before Instruction CNT = Z = After Instruction CNT = Z =
0xFF 0 0x00 1
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IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W) Z 1101 kkkk kkkk The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1 IORLW 0x35 Words: Cycles: Example: Operation: Status Affected: Encoding: Description: MOVF Syntax: Operands: Move f [ label ] 0 f 31 d [0,1] (f) (dest) Z 0010 00df ffff The contents of register 'f' is moved to destination 'd'. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test a file register since status flag Z is affected. 1 1 MOVF FSR, 0 MOVF f,d
Words: Cycles: Example:
Before Instruction W = 0x9A After Instruction W = 0xBF Z=0
After Instruction W = value in FSR register
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR W with f [ label ] 0 f 31 d [0,1] (W).OR. (f) (dest) Z 0001 00df ffff Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. 1 1 IORWF 0x13 0x91 0x13 0x93 0 RESULT, 0 IORWF f,d MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example: Move Literal to W [ label ] k (W) None 1100 kkkk kkkk The eight bit literal 'k' is loaded into the W register. 1 1 MOVLW 0x5A MOVLW k 0 k 255
Words: Cycles: Example:
After Instruction W = 0x5A
Before Instruction RESULT = W = After Instruction RESULT = W = Z =
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MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example: Move W to f [ label ] 0 f 31 (W) (f) None 0000 001f ffff Move data from the W register to register 'f'. 1 1 MOVWF = = = = TEMP_REG 0xFF 0x4F 0x4F 0x4F MOVWF f OPTION Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Load OPTION Register [ label ] None (W) OPTION None 0000 0000 0010 The content of the W register is loaded into the OPTION register. 1 1 OPTION 0x07 0x07 OPTION
Before Instruction TEMP_REG W After Instruction TEMP_REG W
Before Instruction W = After Instruction OPTION =
RETLW Syntax:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None 1000 kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE ;W contains ;table offset ;value. * ;W now has table * ;value. * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table 0x07 value of k8
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None 0000 1 1 NOP 0000 0000 No operation. NOP
Operands: Operation: Status Affected: Encoding: Description:
Words: Cycles: Example:
TABLE
Before Instruction W = After Instruction W =
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RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] RLF 0 f 31 d [0,1] See description below C 0011 01df ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag (STATUS<0>). If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Words: Cycles: Example: 1 1 RLF REG1,0 1110 0110 0 1110 0110 1100 1100 1
register 'f'
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] 0 f 31 d [0,1] See description below C 0011 00df ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag (STATUS<0>). If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C
register 'f'
f,d
RRF f,d
Words: Cycles: Example:
1 1 RRF REG1,0 1110 0110 0 1110 0110 0111 0011 0
Before Instruction REG1 = C = After Instruction REG1 = W = C =
Before Instruction REG1 = C = After Instruction REG1 = W = C =
SLEEP Syntax: Operands: Operation:
Enter SLEEP Mode [label] None 00h WDT; 0 WDT prescaler; if assigned 1 TO; 0 PD TO, PD 0000 0000 0011 Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See section on SLEEP for more details. 1 1 SLEEP SLEEP
Status Affected: Encoding: Description:
Words: Cycles: Example:
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SUBWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from f [label] SUBWF f,d 0 f 31 d [0,1] (f) - (W) (dest) C, DC, Z 0000 10df ffff Status Affected: Encoding: Description: Subtract (2's complement method) the W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 SUBWF REG1, 1 Words: Cycles: Example SWAPF Syntax: Operands: Operation: Swap Nibbles in f [ label ] SWAPF f,d 0 f 31 d [0,1] (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) None 0011 10df ffff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. 1 1 SWAPF REG1, 0xA5 0xA5 0x5A 0
Words: Cycles: Example 1:
Before Instruction REG1 = 3 W = 2 C = ? After Instruction REG1 = 1 W = 2 C = 1 ; result is positive Example 2: Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 = 0 W = 2 C = 1 ; result is zero Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 = 0xFF W = 2 C = 0 ; result is negative
Before Instruction REG1 = After Instruction REG1 = W =
TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description:
Load TRIS Register [ label ] TRIS f = 5, 6 or 7 (W) TRIS register f None 0000 0000 0fff TRIS register 'f' (f = 5, 6, or 7) is loaded with the contents of the W register. 1 1 TRIS PORTB f
Words: Cycles: Example
Before Instruction W = 0xA5 After Instruction TRISB = 0xA5
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XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z 1111 kkkk kkkk The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1 XORLW 0xAF
Words: Cycles: Example:
Before Instruction W = 0xB5 After Instruction W = 0x1A
XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR W with f [ label ] XORWF 0 f 31 d [0,1] (W) .XOR. (f) (dest) Z 0001 10df ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 XORWF REG,1 0xAF 0xB5 0x1A 0xB5 f,d
Words: Cycles: Example
Before Instruction REG = W = After Instruction REG = W =
DS30453D-page 60
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
11.0 DEVELOPMENT SUPPORT
The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board
11.2
MPASM Assembler
The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process.
11.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help
11.3
MPLAB C17 and MPLAB C18 C Compilers
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 61
PIC16C5X
11.4 MPLINK Object Linker/ MPLIB Object Librarian 11.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.
The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user.
11.7
ICEPIC In-Circuit Emulator
11.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool.
The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.
DS30453D-page 62
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
11.8 MPLAB ICD In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime.
11.11 PICDEM 1 Low Cost PICmicro Demonstration Board
The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB.
11.9
PRO MATE II Universal Device Programmer
The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in Stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In Stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.
11.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad.
11.10 PICSTART Plus Entry Level Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 63
PIC16C5X
11.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
11.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
11.15 KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters.
DS30453D-page 64
Preliminary
(c) 2002 Microchip Technology Inc.
24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX
MCRFXXX
MCP2510
TABLE 11-1:
MPLAB(R) Integrated Development Environment
9
9
9
9
9
9
9
9
9
9
9
9
9
99
99
MPLAB(R) C17 C Compiler
Software Tools
MPLAB(R) C18 C Compiler
MPASMTM Assembler/ MPLINKTM Object Linker
9
9
Programmers Debugger Emulators
Demo Boards and Eval Kits
(c) 2002 Microchip Technology Inc.
999
999
99
**
99
99
99
99
99
99
99
99
99
99
99
99
MPLAB(R) ICE In-Circuit Emulator
ICEPICTM In-Circuit Emulator
9
* *
9
9
9
9
9
9
9
MPLAB(R) ICD In-Circuit Debugger
9
**
9
9
9
PICSTART(R) Plus Entry Level Development Programmer
9
**
9
9
9
9
9
9
9
9
9
9
9
9
9
9
PRO MATE(R) II Universal Device Programmer
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary
9 9 9 9 9

PICDEMTM 1 Demonstration Board
PICDEMTM 2 Demonstration Board
9
9
9
9
PICDEMTM 3 Demonstration Board
9
PICDEMTM 14A Demonstration Board
9
PICDEMTM 17 Demonstration Board
9
KEELOQ(R) Evaluation Kit
99
KEELOQ(R) Transponder Kit
microIDTM Programmer's Kit
99
125 kHz microIDTM Developer's Kit
125 kHz Anticollision microIDTM Developer's Kit
9
13.56 MHz Anticollision microIDTM Developer's Kit
9
PIC16C5X
DS30453D-page 65
MCP2510 CAN Developer's Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
9
PIC16C5X
NOTES:
DS30453D-page 66
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
12.0 ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57
Absolute Maximum Ratings() Ambient Temperature under bias ..................................................................................................... -55C to +125C Storage Temperature ....................................................................................................................... -65C to +150C Voltage on VDD with respect to VSS ..........................................................................................................0V to +7.5V Voltage on MCLR with respect to VSS(1) ....................................................................................................0V to +14V Voltage on all other pins with respect to VSS ............................................................................-0.6V to (VDD + 0.6V) Total power dissipation(2) ............................................................................................................................... 800 mW Max. current out of VSS pin ............................................................................................................................. 150 mA Max. current into VDD pin ................................................................................................................................ 100 mA Max. current into an input pin (T0CKI only).................................................................................................... 500 A Input clamp current, IIK (VI < 0 or VI > VDD) .................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................. 20 mA Max. output current sunk by any I/O pin ........................................................................................................... 25 mA Max. output current sourced by any I/O pin ...................................................................................................... 20 mA Max. output current sourced by a single I/O port (PORTA, B or C) .................................................................. 40 mA Max. output current sunk by a single I/O port (PORTA, B or C)........................................................................ 50 mA Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. 2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 67
PIC16C5X
12.1 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial Min Typ Max Units Conditions PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial) Param Symbol No. D001 VDD Characteristic/Device Supply Voltage PIC16C5X-RC PIC16C5X-XT PIC16C5X-10 PIC16C5X-HS PIC16C5X-LP RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) PIC16C5X-RC(3) PIC16C5X-XT PIC16C5X-10 PIC16C5X-HS PIC16C5X-HS PIC16C5X-LP Power-down Current(2) 0.05*
3.0 3.0 4.5 4.5 2.5
-- -- -- -- -- 1.5* VSS --
6.25 6.25 5.5 5.5 6.25 -- -- --
V V V V V V V V/ms Device in SLEEP Mode See Section 5.1 for details on Power-on Reset See Section 5.1 for details on Power-on Reset FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled
D002 D003 D004 D010
VDR VPOR SVDD IDD
-- -- -- -- -- -- -- --
1.8 1.8 4.8 4.8 9.0 15 4.0 0.6
3.3 3.3 10 10 20 32 12 9
mA mA mA mA mA A A A
D020 *
IPD
These parameters are characterized but not tested.
Data in "Typ" column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 68
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
12.2 DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C for industrial Min Typ Max Units Conditions PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial) Param Symbol No. D001 VDD Characteristic/Device Supply Voltage PIC16C5X-RCI PIC16C5X-XTI PIC16C5X-10I PIC16C5X-HSI PIC16C5X-LPI RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) PIC16C5X-RCI(3) PIC16C5X-XTI PIC16C5X-10I PIC16C5X-HSI PIC16C5X-HSI PIC16C5X-LPI Power-down Current(2)
3.0 3.0 4.5 4.5 2.5 -- -- 0.05*
-- -- -- -- -- 1.5* VSS --
6.25 6.25 5.5 5.5 6.25 -- -- --
V V V V V V V V/ms Device in SLEEP mode See Section 5.1 for details on Power-on Reset See Section 5.1 for details on Power-on Reset FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled
D002 D003 D004 D010
VDR VPOR SVDD IDD
-- -- -- -- -- -- -- --
1.8 1.8 4.8 4.8 9.0 15 4.0 0.6
3.3 3.3 10 10 20 40 14 12
mA mA mA mA mA A A A
D020 *
IPD
These parameters are characterized but not tested.
Data in "Typ" column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 69
PIC16C5X
12.3 DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Min Typ Max Units Conditions PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended) Param Symbol No. D001 VDD Characteristic/Device Supply Voltage PIC16C5X-RCE PIC16C5X-XTE PIC16C5X-10E PIC16C5X-HSE PIC16C5X-LPE RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) PIC16C5X-RCE(3) PIC16C5X-XTE PIC16C5X-10E PIC16C5X-HSE PIC16C5X-HSE PIC16C5X-LPE Power-down Current(2)
3.25 3.25 4.5 4.5 2.5 -- -- 0.05*
-- -- -- -- -- 1.5* VSS --
6.0 6.0 5.5 5.5 6.0 -- -- --
V V V V V V V V/ms Device in SLEEP mode See Section 5.1 for details on Power-on Reset See Section 5.1 for details on Power-on Reset FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 16 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.25V, WDT disabled VDD = 3.25V, WDT enabled VDD = 3.25V, WDT disabled
D002 D003 D004 D010
VDR VPOR SVDD IDD
-- -- -- -- -- -- -- --
1.8 1.8 4.8 4.8 9.0 19 5.0 0.8
3.3 3.3 10 10 20 55 22 18
mA mA mA mA mA A A A
D020 *
IPD
These parameters are characterized but not tested.
Data in "Typ" column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 70
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
12.4 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial) PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Min Typ Max Units Conditions
DC CHARACTERISTICS Param Symbol No. D030 VIL
Characteristic/Device Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 (Schmitt Trigger) Input High Voltage I/O ports I/O ports I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 (Schmitt Trigger) Hysteresis of Schmitt Trigger inputs Input Leakage Current(1,2) I/O ports MCLR MCLR T0CKI OSC1
VSS VSS VSS VSS VSS 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD 0.15 VDD*
-- -- -- -- -- -- -- -- -- -- -- -- --
0.2 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD VDD VDD VDD VDD VDD VDD VDD --
V V V V V V V V V V V V V
Pin at hi-impedance PIC16C5X-RC only(3) PIC16C5X-XT, 10, HS, LP For all VDD(4) 4.0V < VDD 5.5V(4) VDD > 5.5V PIC16C5X-RC only(3) PIC16C5X-XT, 10, HS, LP
D040
VIH
D050 D060
VHYS IIL
-1 -5 -- -3 -3
0.5 -- 0.5 0.5 0.5
+1 -- +5 +3 +3
A A A A A
For VDD 5.5V: VSS VPIN VDD, pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16C5X-XT, 10, HS, LP IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, PIC16C5X-RC
D080
VOL
Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage(2) I/O ports OSC2/CLKOUT
-- --
-- --
0.6 0.6
V V
D090
VOH
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 71
PIC16C5X
12.5 DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Min Typ Max Units Conditions DC CHARACTERISTICS Param Symbol No. D030 VIL Characteristic Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 (Schmitt Trigger) Input High Voltage I/O ports I/O ports I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 (Schmitt Trigger) Hysteresis of Schmitt Trigger inputs Input Leakage Current (1,2) I/O ports MCLR MCLR T0CKI OSC1 D080 VOL Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage(2) I/O ports OSC2/CLKOUT
Vss Vss Vss Vss Vss 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD 0.15 VDD*
-- -- -- -- -- -- -- -- -- -- -- -- --
0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD VDD VDD VDD VDD VDD VDD VDD --
V V V V V V V V V V V V V
Pin at hi-impedance PIC16C5X-RC only(3) PIC16C5X-XT, 10, HS, LP For all VDD(4) 4.0V < VDD 5.5V(4) VDD > 5.5 V PIC16C5X-RC only(3) PIC16C5X-XT, 10, HS, LP
D040
VIH
D050 D060
VHYS IIL
-1 -5 -- -3 -3
0.5 -- 0.5 0.5 0.5
+1 -- +5 +3 +3
A A A A A
For VDD 5.5 V: VSS VPIN VDD, pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16C5X-XT, 10, HS, LP IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, PIC16C5X-RC
-- --
-- --
0.6 0.6
V V
D090
VOH
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications.
DS30453D-page 72
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
12.6 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
mc osc os t0 wdt
MCLR oscillator OSC1 T0CKI watchdog timer
P R V Z
Period Rise Valid Hi-impedance
FIGURE 12-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54/55/56/57
Pin CL VSS
CL =
50 pF
for all pins and OSC2 for RC mode
0 - 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 73
PIC16C5X
12.7 Timing Diagrams and Specifications
EXTERNAL CLOCK TIMING - PIC16C54/55/56/57
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
FIGURE 12-2:
TABLE 12-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic External CLKIN Frequency(1) Min DC DC DC DC DC Oscillator Frequency(1) DC 0.1 4.0 4.0 4.0 DC Typ -- -- -- -- -- -- -- -- -- -- -- Max 4.0 10 20 16 40 4.0 4.0 10 20 16 40 Units Conditions
AC Characteristics
Param No. 1A
Symbol FOSC
MHz XT OSC mode MHz 10 MHz mode MHz HS OSC mode (Comm/Ind) MHz HS OSC mode (Ext) kHz LP OSC mode MHz RC OSC mode MHz XT OSC mode MHz 10 MHz mode MHz HS OSC mode (Comm/Ind) MHz HS OSC mode (Ext) kHz LP OSC mode
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 74
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic External CLKIN Period(1) Min 250 100 50 62.5 25 Oscillator Period(1) 250 250 100 50 62.5 25 2 3 Tcy TosL, TosH Instruction Cycle Time(2) Clock in (OSC1) Low or High Time -- 85* 20* 2.0* 4 TosR, TosF Clock in (OSC1) Rise or Fall Time -- -- -- * These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Typ -- -- -- -- -- -- -- -- -- -- -- 4/FOSC -- -- -- -- -- -- Max -- -- -- -- -- -- 10,000 250 250 250 -- -- -- -- -- 25* 25* 50* Units ns ns ns ns s ns ns ns ns ns s -- ns ns s ns ns ns XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator LP oscillator Conditions XT OSC mode 10 MHz mode HS OSC mode (Comm/Ind) HS OSC mode (Ext) LP OSC mode RC OSC mode XT OSC mode 10 MHz mode HS OSC mode (Comm/Ind) HS OSC mode (Ext) LP OSC mode
AC Characteristics
Param No. 1
Symbol TOSC
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 75
PIC16C5X
FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57
Q4 OSC1 10 11 Q1 Q2 Q3
CLKOUT 13 I/O Pin (input) 17 I/O Pin (output) Old Value 15 New Value 18 12 16
14
19
20, 21 Note: Please refer to Figure 12-1 for load conditions.
TABLE 12-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic OSC1 to CLKOUT(1) OSC1 to CLKOUT(1) time(1)
(1)
AC Characteristics Param No. 10 11 12 13 14 15 16 17 18 19 20 21
Symbol TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF
Min -- -- -- --
Typ 15 15 5.0 5.0 -- -- -- -- -- -- 10 10
Max 30** 30** 15** 15** 40** -- -- 100* -- -- 25** 25**
Units ns ns ns ns ns ns ns ns ns ns ns ns
CLKOUT rise
CLKOUT fall time
CLKOUT to Port out Port in valid before
valid(1)
(1)
-- 0.25 TCY+30* 0* valid(2) -- TBD TBD -- --
CLKOUT(1)
Port in hold after CLKOUT
OSC1 (Q1 cycle) to Port out
OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time(2) Port output fall time
(2)
* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x Tosc. 2: Please refer to Figure 12-1 for load conditions.
DS30453D-page 76
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING PIC16C54/55/56/57
VDD MCLR 30 Internal POR 32 DRT Time-out Internal RESET Watchdog Timer Reset 31 34 I/O pin (Note 1) Note 1: Please refer to Figure 12-1 for load conditions. 34
32
32
TABLE 12-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Device Reset Timer Period I/O Hi-impedance from MCLR Low Min 100* 9.0* 9.0* -- Typ -- 18* 18* -- Max -- 30* 30* 100* Units ns ms ms ns Conditions VDD = 5.0V VDD = 5.0V (Comm) VDD = 5.0V (Comm)
AC Characteristics
Param No. 30 31 32 34
Symbol TmcL Twdt TDRT TioZ
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 77
PIC16C5X
FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57
T0CKI 40 41
42 Note: Please refer to Figure 12-1 for load conditions.
TABLE 12-4:
TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic T0CKI High Pulse Width - No Prescaler - With Prescaler T0CKI Low Pulse Width - No Prescaler - With Prescaler T0CKI Period Min Typ Max Units Conditions
AC Characteristics
Param No. 40
Symbol Tt0H
0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N
-- -- -- -- --
-- -- -- -- --
ns ns ns ns ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
41
Tt0L
42
Tt0P
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30453D-page 78
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
13.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A
Absolute Maximum Ratings()
Ambient Temperature under bias ..................................................................................................... -55C to +125C Storage Temperature ....................................................................................................................... -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................ 0 to +7.5V Voltage on MCLR with respect to VSS(1) ...................................................................................................... 0 to +14V Voltage on all other pins with respect to VSS ............................................................................-0.6V to (VDD + 0.6V) Total power dissipation(2) ............................................................................................................................... 800 mW Max. current out of VSS pin ............................................................................................................................. 150 mA Max. current into VDD pin .................................................................................................................................. 50 mA Max. current into an input pin (T0CKI only) .............................................................................................................. 500 A Input clamp current, IIK (VI < 0 or VI > VDD) ...............................................................................................................20 mA Output clamp current, IOK (V0 < 0 or V0 > VDD) ........................................................................................................20 mA Max. output current sunk by any I/O pin ........................................................................................................... 25 mA Max. output current sourced by any I/O pin ...................................................................................................... 20 mA Max. output current sourced by a single I/O port (PORTA or B) ....................................................................... 40 mA Max. output current sunk by a single I/O port (PORTA or B) ............................................................................ 50 mA Note 1: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss. 2: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 79
PIC16C5X
13.1 DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial) PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Min Typ Max Units Conditions
PIC16LCR54A-04 PIC16LCR54A-04I (Commercial, Industrial) PIC16CR54A-04, 10, 20 PIC16CR54A-04I, 10I, 20I (Commercial, Industrial) Param No. D001 D001 D001A D002 D003 D004 VDR VPOR SVDD IDD D005 D005A PIC16CR54A Symbol VDD Characteristic/Device Supply Voltage PIC16LCR54A PIC16CR54A RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) PICLCR54A
2.0 2.5 4.5 -- -- 0.05*
-- -- -- 1.5* VSS --
6.25 6.25 5.5 -- -- --
V V V V V V/ms RC and XT modes HS mode Device in SLEEP mode See Section 5.1 for details on Power-on Reset See Section 5.1 for details on Power-on Reset Fosc = 32 kHz, VDD = 2.0V Fosc = 32 kHz, VDD = 6.0V RC(3) and XT modes: FOSC = 4.0 MHz, VDD = 6.0V FOSC = 4.0 MHz, VDD = 3.0V FOSC = 200 kHz, VDD = 2.5V HS mode: FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V
-- -- -- -- -- -- --
10 -- 2.0 0.8 90 4.8 9.0
20 70 3.6 1.8 350 10 20
A A mA mA A mA mA
Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 80
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
13.1 DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial) PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Min Typ Max Units Conditions
PIC16LCR54A-04 PIC16LCR54A-04I (Commercial, Industrial) PIC16CR54A-04, 10, 20 PIC16CR54A-04I, 10I, 20I (Commercial, Industrial) Param No. D006 Symbol IPD Characteristic/Device Power-down Current(2) PIC16LCR54A-Commercial
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1.0 2.0 3.0 5.0 1.0 2.0 3.0 5.0 1.0 2.0 3.0 3.0 5.0 1.0 2.0 3.0 3.0 5.0
6.0 8.0* 15 25 6.0 8.0* 15 25 8.0 10* 20* 18 45 8.0 10* 20* 18 45
A A A A A A A A A A A A A A A A A A
VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 4.0V, WDT enabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 4.0V, WDT enabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled
D006A
PIC16CR54A-Commercial
D007
PIC16LCR54A-Industrial
D007A
PIC16CR54A-Industrial
Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 81
PIC16C5X
13.2 DC Characteristics:PIC16CR54A-04E, 10E, 20E (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Min Typ Max Units Conditions PIC16CR54A-04E, 10E, 20E (Extended) Param Symbol No. D001 VDD Characteristic Supply Voltage RC, XT and LP modes HS mode RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset
3.25 4.5 -- --
-- -- 1.5* VSS --
6.0 5.5 -- -- --
V V V V V/ms Device in SLEEP mode See Section 5.1 for details on Power-on Reset See Section 5.1 for details on Power-on Reset FOSC = 4.0 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 16 MHz, VDD = 5.5V VDD = 3.25V, WDT enabled VDD = 3.25V, WDT disabled
D002 D003 D004 D010
VDR VPOR SVDD IDD
VDD Rise Rate to ensure Power- 0.05* on Reset Supply Current(2) RC(3) and XT modes HS mode HS mode Power-down Current(2) -- -- -- -- --
1.8 4.8 9.0 5.0 0.8
3.3 10 20 22 18
mA mA mA A A
D020 *
IPD
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 82
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
13.3 DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial) PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Min Typ Max Units Conditions
DC CHARACTERISTICS Param Symbol No. D030 VIL
Characteristic Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Input High Voltage I/O ports I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs Input Leakage Current(1,2) I/O ports MCLR MCLR T0CKI OSC1
VSS VSS VSS VSS VSS 2.0 0.6 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.15 VDD*
-- -- -- -- -- -- -- -- -- -- -- --
0.2 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD VDD VDD VDD VDD VDD VDD --
V V V V V V V V V V V V
Pin at hi-impedance RC mode only(3) XT, HS and LP modes VDD = 3.0V to 5.5V(4) Full VDD range(4) RC mode only(3) XT, HS and LP modes
D040
VIH
D050 D060
VHYS IIL
-1.0 -5.0 -- -3.0 -3.0
-- -- 0.5 0.5 0.5
+1.0 -- +5.0 +3.0 +3.0
A A A A A
For VDD 5.5V: VSS VPIN VDD, pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP modes IOL = 10 mA, VDD = 6.0V IOL = 1.9 mA, VDD = 6.0V, RC mode only IOH = -4.0 mA, VDD = 6.0V IOH = -0.8 mA, VDD = 6.0V, RC mode only
D080
VOL
Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage(2) I/O ports OSC2/CLKOUT
-- --
-- --
0.5 0.5
V V
D090
VOH
VDD - 0.5 VDD - 0.5
-- --
-- --
V V
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 83
PIC16C5X
13.4 DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Min Typ Max Units Conditions DC CHARACTERISTICS Param Symbol No. D030 VIL Characteristic Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Input High Voltage I/O ports I/O ports I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs Input Leakage Current(1,2) I/O ports MCLR MCLR T0CKI OSC1 D080 VOL Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage(2) I/O ports OSC2/CLKOUT
Vss Vss Vss Vss Vss 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD 0.15 VDD*
-- -- -- -- -- -- -- -- -- -- -- -- --
0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD VDD VDD VDD VDD VDD VDD VDD --
V V V V V V V V V V V V V
Pin at hi-impedance RC mode only(3) XT, HS and LP modes For all VDD(4) 4.0V < VDD 5.5V(4) VDD > 5.5V RC mode only(3) XT, HS and LP modes
D040
VIH
D050 D060
VHYS IIL
-1.0 -5.0 -- -3.0 -3.0
0.5 -- 0.5 0.5 0.5
+1.0 -- +5.0 +3.0 +3.0
A A A A A
For VDD 5.5V: VSS VPIN VDD, pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP modes IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, RC mode only IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, RC mode only
-- --
-- --
0.6 0.6
V V
D090
VOH
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications.
DS30453D-page 84
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
13.5 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
mc osc os t0 wdt
MCLR oscillator OSC1 T0CKI watchdog timer
P R V Z
Period Rise Valid Hi-impedance
FIGURE 13-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16CR54A
Pin CL VSS
CL = 50 pF 0 -15 pF
for all pins and OSC2 for RC modes for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 85
PIC16C5X
13.6 Timing Diagrams and Specifications
EXTERNAL CLOCK TIMING - PIC16CR54A
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
FIGURE 13-2:
TABLE 13-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic External CLKIN Frequency(1) Min DC DC DC DC DC Oscillator Frequency
(1)
AC Characteristics
Param No.
Symbol FOSC
Typ -- -- -- -- -- -- -- -- -- -- --
Max 4.0 4.0 10 20 200 4.0 4.0 4.0 10 20 200
Units
Conditions
MHz XT OSC mode MHz HS OSC mode (04) MHz HS OSC mode (10) MHz HS OSC mode (20) kHz LP OSC mode MHz RC OSC mode MHz XT OSC mode MHz HS OSC mode (04) MHz HS OSC mode (10) MHz HS OSC mode (20) kHz LP OSC mode
DC 0.1 4.0 4.0 4.0 5.0
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 86
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic External CLKIN Period(1) Min 250 250 100 50 5.0 Oscillator Period(1) 250 250 250 100 50 5.0 2 3 Tcy Instruction Cycle Time
(2)
AC Characteristics
Param No. 1
Symbol TOSC
Typ -- -- -- -- -- -- -- -- -- -- -- 4/FOSC -- -- -- -- -- --
Max -- -- -- -- -- -- 10,000 250 250 250 200 -- -- -- -- 25* 25* 50*
Units ns ns ns ns s ns ns ns ns ns s -- ns ns s ns ns ns
Conditions XT OSC mode HS OSC mode (04) HS OSC mode (10) HS OSC mode (20) LP OSC mode RC OSC mode XT OSC mode HS OSC mode (04) HS OSC mode (10) HS OSC mode (20) LP OSC mode XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator LP oscillator
-- 50* 20* 2.0* -- -- --
TosL, TosH Clock in (OSC1) Low or High Time
4
TosR, TosF Clock in (OSC1) Rise or Fall Time
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 87
PIC16C5X
FIGURE 13-3: CLKOUT AND I/O TIMING - PIC16CR54A
Q4 OSC1
10 11
Q1
Q2
Q3
CLKOUT
13 14 19 18 12 16
I/O Pin (input)
17 15 New Value 20, 21
I/O Pin (output)
Old Value
Note: Please refer to Figure 13.1 for load conditions.
TABLE 13-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic OSC1 to CLKOUT(1) OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time
(1) (1) (1)
AC Characteristics
Param No. 10 11 12 13 14 15 16 17 18 19 20 21 * **
Symbol TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF
Min -- -- -- -- -- 0.25 TCY+30* 0*
(2)
Typ 15 15 5.0 5.0 -- -- -- -- -- -- 10 10
Max 30** 30** 15** 15** 40** -- -- 100* -- -- 25** 25**
Units ns ns ns ns ns ns ns ns ns ns ns ns
CLKOUT to Port out valid(1) Port in valid before CLKOUT(1) Port in hold after CLKOUT
(1)
OSC1 (Q1 cycle) to Port out valid
-- TBD TBD -- --
OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time(2) Port output fall time(2)
These parameters are characterized but not tested. These parameters are design targets and are not tested. No characterization data available at this time. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Please refer to Figure 13.1 for load conditions.
DS30453D-page 88
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 13-4:
VDD MCLR 30 Internal POR 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 I/O pin (Note 1) Note 1: Please refer to Figure 13.1 for load conditions. 34
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A
32
32
TABLE 13-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial AC Characteristics -40C TA +85C for industrial -40C TA +125C for extended Param No. 30 31 32 34 * Symbol TmcL Twdt TDRT TioZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Device Reset Timer Period I/O Hi-impedance from MCLR Low Min 1.0* 7.0* 7.0* -- Typ -- 18* 18* -- Max -- 40* 30* 1.0* Units s ms ms s Conditions VDD = 5.0V VDD = 5.0V (Comm) VDD = 5.0V (Comm)
These parameters are characterized but not tested.
Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 89
PIC16C5X
FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC16CR54A
T0CKI 40 41
42 Note: Please refer to Figure 13.1 for load conditions.
TABLE 13-4:
TIMER0 CLOCK REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic T0CKI High Pulse Width - No Prescaler - With Prescaler T0CKI Low Pulse Width - No Prescaler - With Prescaler T0CKI Period Min Typ Max Units Conditions
AC Characteristics
Param Symbol No. 40 Tt0H
0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N
-- -- -- -- --
-- -- -- -- --
ns ns ns ns ns
41
Tt0L
42
Tt0P
Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30453D-page 90
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
14.0 DEVICE CHARACTERIZATION - PIC16C54/55/56/57/CR54A
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. "Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 14-1:
FOSC FOSC (25C) 1.10 1.08 1.06 1.04 1.02 1.00 0.98
TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
Frequency normalized to +25C
REXT 10 k CEXT = 100 pF
VDD = 5.5V 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 T(C) 40 50 60 70
TABLE 14-1:
CEXT 20 pF
RC OSCILLATOR FREQUENCIES
REXT 3.3K 5K 10K 100K 5 MHz 3.8 MHz 2.2 MHz 262 kHz 1.6 MHz 1.2 MHz 684 kHz 71 kHz 660 kHz 484 kHz 267 kHz 29 kHz Average FOSC @ 5 V, 25C 27% 21% 21% 31% 13% 13% 18% 25% 10% 14% 15% 19%
100 pF
3.3K 5K 10K 100K
300 pF
3.3K 5.0K 10K 100K
The frequencies are measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviations from the average value for VDD = 5V.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 91
PIC16C5X
FIGURE 14-2: TYPICAL RC OSC FREQUENCY vs. VDD, CEXT = 20 PF FIGURE 14-3: TYPICAL RC OSC FREQUENCY vs. VDD, CEXT = 100 PF
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
5.5 R = 3.3K 5.0
1.8 R = 3.3K 1.6
4.5 R = 5K
1.4 R = 5K
4.0
1.2 Fosc (MHz)
3.5 Fosc (MHz)
1.0
3.0 R = 10K 2.5
0.8 R = 10K 0.6 Measured on DIP Packages, T = 25C
2.0 Measured on DIP Packages, T = 25C 1.5
0.4
0.2 R = 100K
1.0 0.0 3.0 0.5 R = 100K 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 6.0
0.0 3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30453D-page 92
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-4: TYPICAL RC OSC FREQUENCY vs. VDD, CEXT = 300 PF FIGURE 14-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
2.5
800 2.0 T = 25C 1.5 IPD (A) R = 5K
700
R = 3.3K
600
500 Fosc (kHz)
1.0
400 0.5
300
R = 10K
200 Measured on DIP Packages, T = 25C 100 R = 100K 0 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
0.0 2.5
3.0
3.5
4.0
4.5
5.0
5.5 6.0
VDD (Volts)
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 93
PIC16C5X
FIGURE 14-6: MAXIMUM IPD vs. VDD, WATCHDOG DISABLED FIGURE 14-8: MAXIMUM IPD vs. VDD, WATCHDOG ENABLED
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
100
60
50 +125C 10 +85C +70C 0C Ipd (A) 30 -40C IPD (A)
+125C -40C +70C
40
-55C +85C
1
-55C
20
0C
10
0 2.5 3.0
3.5
4.0
4.5 5.0
5.5 6.0
6.5
7.0
0 2.5
3.0
3.5
VDD (Volts)
4.0 4.5 5.0 VDD (Volts)
5.5
6.0
6.5 7.0
FIGURE 14-7:
TYPICAL IPD vs. VDD, WATCHDOG ENABLED
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
IPD, with WDT enabled, has two components: The leakage current, which increases with higher temperature, and the operating current of the WDT logic, which increases with lower temperature. At -40C, the latter dominates explaining the apparently anomalous behavior.
20 18 16 14 T = 25C 12 IPD (A) 10 8 6 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
DS30453D-page 94
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
2.00 1.80 1.60 VTH (Volts) 1.40 1.20 1.00 0.80 0.60
40 Min (- C to + 85 C ) - 40 C M ax ( to +85 C )
25 Typ (+
C )
2.5
3.0
3.5
4.0
4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 14-10:
VIH, VIL OF MCLR, T0CKI AND OSC1 (RC MODE) vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
4.5 4.0 3.5 VIH, VIL (Volts) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 Note: 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
to +85C) VIL max (-40C VIH typ +25C
C) VIL min (-40C to +85
C) +8 5 C to (-40 max VIH C + 25 ) typ V IH 85C to + 0C (-4 min VIH
These input pins have Schmitt Trigger input buffers.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 95
PIC16C5X
FIGURE 14-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (XT, HS, AND LP MODES) vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
3.4 3.2 3.0 2.8 2.6 VTH (Volts) 2.4 2.2 2.0 1.8 1.6 1.4 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
Min
Ma x to 0 C (- 4
(+ Typ
+85
)
C)
25C
) 5C o +8 C t (- 4 0
FIGURE 14-12:
TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10
1.0 IDD (mA) 0.1
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5
0.01 10K 100K 1M External Clock Frequency (Hz) 10M 100M
DS30453D-page 96
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-13: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -40C TO +85C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10
1.0
IDD (mA)
0.1
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5
0.01 10K 100K 1M External Clock Frequency (Hz) 10M 100M
FIGURE 14-14:
MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK -55C TO +125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10
1.0
IDD (mA)
0.1
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5
0.01 10K 100K 1M External Clock Frequency (Hz) 10M 100M
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 97
PIC16C5X
FIGURE 14-15: WDT TIMER TIME-OUT PERIOD vs. VDD(1) FIGURE 14-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
50
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
9000
45
8000
40
Max -40C
7000
35
WDT period (ms)
6000
30
Max +85C
gm (A/V)
5000
Typ +25C
25
Max +70C
4000
20
Typ +25C
3000
Min +85C
15
MIn 0C
2000
10
MIn -40C
100
7.0
5 2.0
3.0
4.0
5.0
6.0
VDD (Volts)
0 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts)
Note 1: Prescaler set to 1:1.
DS30453D-page 98
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD FIGURE 14-18: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
45
2500
40
Max -40C Max -40C
35
2000
30 1500 gm (A/V) 25 gm (A/V)
Typ +25C Typ +25C
20
1000
15
Min +85C
10
Min +85C
500
5 0 2.0 0 2.0 3.0 4.0 5.0 6.0 7.0 3.0 4.0 5.0 6.0 7.0
VDD (Volts)
VDD (Volts)
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 99
PIC16C5X
FIGURE 14-19: PORTA, B AND C IOH vs. VOH, VDD = 3 V FIGURE 14-20: PORTA, B AND C IOH vs. VOH, VDD = 5 V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
0
0
Min +85C
-5
Min +85C
-10
IOH (mA)
-10 IOH (mA) -20
Typ +25C
Typ +25C
-15
Max -40C
-30
Max -40C
-20
-40 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (Volts) VOH (Volts) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DS30453D-page 100
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-21: PORTA, B AND C IOL vs. VOL, VDD = 3 V FIGURE 14-22: PORTA, B AND C IOL vs. VOL, VDD = 5 V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
45
Max -40C
90
40
80
Max -40C
35
70
30
60
Typ +25C
IOL (mA)
Typ +25C
20
IOL (mA)
25
50
40
Min +85C
15
Min +85C
30
10
20
5
10
0 0.0
0 0.5 1.0 1.5 VOL (Volts) 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts)
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 101
PIC16C5X
TABLE 14-2: INPUT CAPACITANCE FOR PIC16C54/56
Typical Capacitance (pF) Pin 18L PDIP RA port RB port MCLR OSC1 OSC2/CLKOUT T0CKI 5.0 5.0 17.0 4.0 4.3 3.2 18L SOIC 4.3 4.3 17.0 3.5 3.5 2.8
All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account.
TABLE 14-3:
INPUT CAPACITANCE FOR PIC16C55/57
Typical Capacitance (pF) 28L PDIP (600 mil) 5.2 5.6 5.0 17.0 6.6 4.6 4.5 28L SOIC 4.8 4.7 4.1 17.0 3.5 3.5 3.5
Pin
RA port RB port RC port MCLR OSC1 OSC2/CLKOUT T0CKI
All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account.
DS30453D-page 102
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
15.0 ELECTRICAL CHARACTERISTICS - PIC16C54A
Absolute Maximum Ratings() Ambient temperature under bias...................................................................................................... -55C to +125C Storage temperature ....................................................................................................................... -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................ 0 to +7.5V Voltage on MCLR with respect to VSS.......................................................................................................... 0 to +14V Voltage on all other pins with respect to VSS ............................................................................-0.6V to (VDD + 0.6V) Total power dissipation(1) ............................................................................................................................... 800 mW Max. current out of VSS pin ............................................................................................................................. 150 mA Max. current into VDD pin ................................................................................................................................ 100 mA Max. current into an input pin (T0CKI only) .............................................................................................................. 500 A Input clamp current, IIK (VI < 0 or VI > VDD)..............................................................................................................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ........................................................................................................20 mA Max. output current sunk by any I/O pin ........................................................................................................... 25 mA Max. output current sourced by any I/O pin ...................................................................................................... 20 mA Max. output current sourced by a single I/O port (PORTA or B) ....................................................................... 50 mA Max. output current sunk by a single I/O port (PORTA or B) ............................................................................ 50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 103
PIC16C5X
15.1 DC Characteristics: PIC16C54A-04, 10, 20 (Commercial) PIC16C54A-04I, 10I, 20I (Industrial) PIC16LC54A-04 (Commercial) PIC16LC54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Min Typ Max Units Conditions
PIC16LC54A-04 PIC16LC54A-04I (Commercial, Industrial) PIC16C54A-04, 10, 20 PIC16C54A-04I, 10I, 20I (Commercial, Industrial) Param Symbol No. VDD D001 D001A D002 D003 D004 VDR VPOR SVDD IDD D005 Characteristic/Device Supply Voltage PIC16LC54A PIC16C54A RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) PIC16LC5X
3.0 2.5 3.0 4.5 -- -- 0.05*
-- -- -- -- 1.5* Vss --
6.25 6.25 6.25 5.5 -- -- --
V V V V V V
XT and RC modes LP mode RC, XT and LP modes HS mode Device in SLEEP mode See Section 5.1 for details on Power-on Reset
V/ms See Section 5.1 for details on Power-on Reset
-- -- --
0.5 11 11 1.8 2.4 4.5 14 17
2.5 27 35 2.4 8.0 16 29 37
mA A A mA mA mA A A
FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes FOSC = 32 kHz, VDD = 2.5V, WDT disabled, LP mode, Commercial FOSC = 32 kHz, VDD = 2.5V, WDT disabled, LP mode, Industrial FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes FOSC = 10 MHz, VDD = 5.5V, HS mode FOSC = 20 MHz, VDD = 5.5V, HS mode FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP mode, Commercial FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP mode, Industrial
D005A
PIC16C5X
-- -- -- -- --
Legend: *
Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in "Typ" column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 104
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
15.1 DC Characteristics: PIC16C54A-04, 10, 20 (Commercial) PIC16C54A-04I, 10I, 20I (Industrial) PIC16LC54A-04 (Commercial) PIC16LC54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Min Typ Max Units Conditions
PIC16LC54A-04 PIC16LC54A-04I (Commercial, Industrial) PIC16C54A-04, 10, 20 PIC16C54A-04I, 10I, 20I (Commercial, Industrial) Param Symbol No. IPD D006 Characteristic/Device Power-down Current(2) PIC16LC5X
-- -- -- -- -- -- -- --
2.5 0.25 2.5 0.25 4.0 0.25 5.0 0.3
12 4.0 14 5.0 12 4.0 14 5.0
A A A A A A A A
VDD = 2.5V, WDT enabled, Commercial VDD = 2.5V, WDT disabled, Commercial VDD = 2.5V, WDT enabled, Industrial VDD = 2.5V, WDT disabled, Industrial VDD = 3.0V, WDT enabled, Commercial VDD = 3.0V, WDT disabled, Commercial VDD = 3.0V, WDT enabled, Industrial VDD = 3.0V, WDT disabled, Industrial
D006A
PIC16C5X
Legend: *
Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in "Typ" column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 105
PIC16C5X
15.2 DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended) PIC16LC54A-04E (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Characteristic Supply Voltage PIC16LC54A PIC16C54A VDR VPOR SVDD IDD D010 RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) PIC16LC54A -- -- -- -- D010A PIC16C54A -- -- -- Legend: * 0.5 11 11 11 1.8 4.8 9.0 25 27 35 37 3.3 10 20 mA A A A mA mA mA FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes FOSC = 32 kHz, VDD = 2.5V, LP mode, Commercial FOSC = 32 kHz, VDD = 2.5V, LP mode, Industrial FOSC = 32 kHz, VDD = 2.5V, LP mode, Extended FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes FOSC = 10 MHz, VDD = 5.5V, HS mode FOSC = 20 MHz, VDD = 5.5V, HS mode 3.0 2.5 3.5 4.5 -- -- 0.05* -- -- -- -- 1.5* Vss -- 6.25 6.25 5.5 5.5 -- -- -- V V V V V V XT and RC modes LP mode RC and XT modes HS mode Device in SLEEP mode See Section 5.1 for details on Power-on Reset Min Typ Max Units Conditions
PIC16LC54A-04E (Extended) PIC16C54A-04E, 10E, 20E (Extended) Param Symbol No. VDD D001 D001A D002 D003 D004
V/ms See Section 5.1 for details on Power-on Reset
Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 106
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
15.2 DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended) PIC16LC54A-04E (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended Characteristic Power-down Current(2) PIC16LC54A -- -- D020A Legend: * PIC16C54A -- -- 2.5 0.25 5.0 0.8 15 7.0 22 18* A A A A VDD = 2.5V, WDT enabled, Extended VDD = 2.5V, WDT disabled, Extended VDD = 3.5V, WDT enabled VDD = 3.5V, WDT disabled Min Typ Max Units Conditions PIC16LC54A-04E (Extended) PIC16C54A-04E, 10E, 20E (Extended) Param Symbol No. IPD D020
Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 107
PIC16C5X
15.3 DC Characteristics: PIC16LV54A-02 (Commercial) PIC16LV54A-02I (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -20C TA +85C for industrial Min Typ Max Units Conditions
PIC16LV54A-02 PIC16LV54A-02I (Commercial, Industrial) Param Symbol No. D001 VDD D002 D003 D004 D010 VDR VPOR SVDD IDD Characteristic Supply Voltage RC and XT modes RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(2) RC(3) and XT modes LP mode, Commercial LP mode, Industrial Power-down Current(2,4) Commercial Commercial Industrial Industrial
2.0 -- -- 0.05*
-- 1.5* Vss --
3.8 -- -- --
V V V Device in SLEEP mode See Section 5.1 for details on Power-on Reset
V/ms See Section 5.1 for details on Power-on Reset mA A A A A A A FOSC = 2.0 MHz, VDD = 3.0V FOSC = 32 kHz, VDD = 2.5V WDT disabled FOSC = 32 kHz, VDD = 2.5V WDT disabled VDD = 2.5V, WDT enabled VDD = 2.5V, WDT disabled VDD = 2.5V, WDT enabled VDD = 2.5V, WDT disabled
-- -- -- -- -- -- --
0.5 11 14 2.5 0.25 3.5 0.3
-- 27 35 12 4.0 14 5.0
D020
IPD
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. 4: The oscillator start-up time can be as much as 8 seconds for XT and LP oscillator selection on wake-up from SLEEP mode or during initial power-up.
DS30453D-page 108
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
15.4
DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial) PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial) PIC16C54A-04E, 10E, 20E, PIC16LC54A-04E (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -20C TA +85C for industrial-PIC16LV54A-02I -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS
Param Symbol No.
D030 VIL
Characteristic
Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Input High Voltage I/O ports I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs Input Leakage Current(1,2) I/O ports MCLR MCLR T0CKI OSC1
VSS VSS VSS VSS VSS 0.2 VDD + 1 2.0 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD 0.15 VDD*
-- -- -- -- -- -- -- -- -- -- -- --
0.2 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD VDD VDD VDD VDD VDD VDD --
V V V V
Pin at hi-impedance
RC mode only(3) XT, HS and LP modes For all VDD(4) 4.0V < VDD 5.5V(4) RC mode only(3) XT, HS and LP modes
D040
VIH
V V V V V V V
D050 D060
VHYS IIL
-1.0 -5.0 -- -3.0 -3.0
0.5 -- 0.5 0.5 0.5
+1.0 +5.0 +3.0 +3.0 --
A A A A A
For VDD 5.5V: VSS VPIN VDD, pin at hi-impedance VPIN = VSS +0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP modes IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, RC mode only IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, RC mode only
D080
VOL
Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage(2) I/O ports OSC2/CLKOUT
-- --
-- --
0.6 0.6
V V
VOH
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 109
PIC16C5X
15.5 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
mc osc os t0 wdt
MCLR oscillator OSC1 T0CKI watchdog timer
P R V Z
Period Rise Valid Hi-impedance
FIGURE 15-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54A
Pin CL VSS
CL = 50 pF
for all pins and OSC2 for RC modes
0 -15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1
DS30453D-page 110
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
15.6 Timing Diagrams and Specifications
FIGURE 15-2: EXTERNAL CLOCK TIMING - PIC16C54A
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 15-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -20C TA +85C for industrial - PIC16LV54A-02I -40C TA +125C for extended Characteristic External CLKIN Frequency(1) Min DC DC DC DC DC DC Oscillator Frequency
(1)
AC Characteristics
Param No.
Symbol FOSC
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max 4.0 2.0 4.0 10 20 200 4.0 2.0 4.0 2.0 4.0 10 20 200
Units
Conditions
MHz XT OSC mode MHz XT OSC mode (PIC16LV54A) MHz HS OSC mode (04) MHz HS OSC mode (10) MHz HS OSC mode (20) kHz LP OSC mode MHz RC OSC mode MHz RC OSC mode (PIC16LV54A) MHz XT OSC mode MHz XT OSC mode (PIC16LV54A) MHz HS OSC mode (04) MHz HS OSC mode (10) MHz HS OSC mode (20) kHz LP OSC mode
DC DC 0.1 0.1 4.0 4.0 4.0 5.0
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 111
PIC16C5X
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -20C TA +85C for industrial - PIC16LV54A-02I -40C TA +125C for extended Characteristic External CLKIN Period(1) Min 250 500 250 100 50 5.0 Oscillator Period
(1)
AC Characteristics
Param No. 1
Symbol TOSC
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4/FOSC -- -- -- -- -- --
Max -- -- -- -- -- -- -- -- 10,000 -- 250 250 250 200 -- -- -- -- 25* 25* 50*
Units ns ns ns ns ns s ns ns ns ns ns ns ns s -- ns ns s ns ns ns
Conditions XT OSC mode XT OSC mode (PIC16LV54A) HS OSC mode (04) HS OSC mode (10) HS OSC mode (20) LP OSC mode RC OSC mode RC OSC mode (PIC16LV54A) XT OSC mode XT OSC mode (PIC16LV54A) HS OSC mode (04) HS OSC mode (10) HS OSC mode (20) LP OSC mode XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator LP oscillator
250 500 250 500 250 100 50 5.0
2 3
Tcy
Instruction Cycle Time
(2)
-- 85* 20* 2.0* -- -- --
TosL, TosH Clock in (OSC1) Low or High Time
4
TosR, TosF Clock in (OSC1) Rise or Fall Time
*
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 112
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 15-3: CLKOUT AND I/O TIMING - PIC16C54A
Q4 OSC1 10 11 Q1 Q2 Q3
CLKOUT 13 I/O Pin (input) 17 I/O Pin (output) Old Value 15 New Value 18 12 16
14
19
20, 21 Note: Please refer to Figure 15-1 for load conditions.
TABLE 15-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -20C TA +85C for industrial - PIC16LV54A-02I -40C TA +125C for extended Characteristic OSC1 to CLKOUT(1) OSC1 to CLKOUT CLKOUT rise time
(1) (1)
AC Characteristics
Param No. 10 11 12 13 14 15 16 17 18 19 20 21
Symbol TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF
Min -- -- -- --
Typ 15 15 5.0 5.0 -- -- -- -- -- -- 10 10
Max 30** 30** 15** 15** 40** -- -- 100* -- -- 25** 25**
Units ns ns ns ns ns ns ns ns ns ns ns ns
CLKOUT fall time(1) CLKOUT to Port out valid
(1) (1)
-- 0.25 TCY+30* 0* -- TBD TBD -- --
Port in valid before CLKOUT Port in hold after CLKOUT
(1)
OSC1 (Q1 cycle) to Port out valid(2) OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time(2) Port output fall time
(2)
* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Please refer to Figure 15-1 for load conditions.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 113
PIC16C5X
FIGURE 15-4:
VDD MCLR 30 Internal POR 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 I/O pin (Note 1) Note 1: Please refer to Figure 15-1 for load conditions. 34
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54A
32
32
TABLE 15-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial AC Characteristics -40C TA +85C for industrial -20C TA +85C for industrial - PIC16LV54A-02I -40C TA +125C for extended Param No. 30 31 32 34 * Symbol TmcL Twdt TDRT TioZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Device Reset Timer Period I/O Hi-impedance from MCLR Low Min 100* 1 9.0* 9.0* -- -- Typ -- -- 18* 18* -- -- Max -- -- 30* 30* 100* 1s Units ns s ms ms ns -- Conditions VDD = 5.0V VDD = 5.0V (PIC16LV54A only) VDD = 5.0V (Comm) VDD = 5.0V (Comm) (PIC16LV54A only)
These parameters are characterized but not tested.
Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30453D-page 114
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 15-5: TIMER0 CLOCK TIMINGS - PIC16C54A
T0CKI 40 41
42 Note: Please refer to Figure 15-1 for load conditions.
TABLE 15-4:
TIMER0 CLOCK REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -20C TA +85C for industrial - PIC16LV54A-02I -40C TA +125C for extended Characteristic T0CKI High Pulse Width - No Prescaler - With Prescaler T0CKI Low Pulse Width - No Prescaler - With Prescaler T0CKI Period Min Typ Max Units Conditions
AC Characteristics
Param Symbol No. 40 Tt0H
0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N
-- -- -- -- --
-- -- -- -- --
ns ns ns ns ns
41
Tt0L
42
Tt0P
Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 115
PIC16C5X
NOTES:
DS30453D-page 116
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
16.0 DEVICE CHARACTERIZATION - PIC16C54A
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. "Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 16-1:
Fosc Fosc (25C) 1.10 1.08 1.06 1.04 1.02 1.00 0.98
TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
Frequency normalized to +25C
REXt 10 kW CEXT = 100 pF
VDD = 5.5V 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 T(C) 40 50 60 70
TABLE 16-1:
CEXT 20 pF
RC OSCILLATOR FREQUENCIES
REXT 3.3K 5K 10K 100K 5 MHz 3.8 MHz 2.2 MHz 262 kHz 1.6 MHz 1.2 MHz 684 kHz 71 kHz 660 kHz 484 kHz 267 kHz 29 kHz Average Fosc @ 5 V, 25C 27% 21% 21% 31% 13% 13% 18% 25% 10% 14% 15% 19%
100 pF
3.3K 5K 10K 100K
300 pF
3.3K 5.0K 10K 100K
The frequencies are measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 117
PIC16C5X
FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25C
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
6
R=3.3K
5
R=5K
4 FOSC (MHz)
3
R=10K
2
1
R=100K
0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
FIGURE 16-3:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
6
R=3.3K
5
R=5K
4 FOSC (MHz)
3
R=10K
2
1
R=100K
0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5
5.0
5.5
6.0
DS30453D-page 118
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25C
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
700 R=3.3K 600
500 R=5K FOSC (kHz) 400
300 R=10K 200
100 R=100K 0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 119
PIC16C5X
FIGURE 16-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
2.5 2.0 IPD (A) 1.5 1.0 0.5 0
2.5
3.0
3.5
4.0
4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 16-6:
TYPICAL IPD VS. VDD, WATCHDOG ENABLED (25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
25.00
20.00
15.00
10.00
5.00
0.00 2.5 3 3.5 4 VDD (Volts) 4.5 5 5.5 6
DS30453D-page 120
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS - VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
2.0 1.8 1.6 VTH (Volts) 1.4 1.2 1.0 0.8 0.6
40 C to +85 C) Max (- 40 C to +85 C )
25 Typ (+
C )
Min (-
2.5
3.0
3.5
4.0
4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 16-8:
VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
3.4 3.2 3.0 2.8 2.6 VTH (Volts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
Min
Ma x 0 (- 4 o +8 C t 5 C )
(+ Typ
) 25 C
5 o +8 C t -40 (
C)
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 121
PIC16C5X
FIGURE 16-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
4.5 4.0 3.5 VIH, VIL (Volts) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
VIL max (-40 C to +85C)
) 5C o +8 C t (-40 max VIH C + 25 ) typ VIH 85C to + 0C (-4 min VIH
Vil typ +25C
VIL min (-40C to +8 5C)
Note:
These input pins have Schmitt Trigger input buffers.
DS30453D-page 122
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-10: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000 IDD (A)
100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
10 0.1 1 Freq (MHz) 10
FIGURE 16-11:
MAXIMUM IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, -40C to +85C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000 IDD (A)
100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
10 0.1
1 Freq (MHz)
10
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 123
PIC16C5X
FIGURE 16-12: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000 IDD (A)
100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
10 0.01
0.1 Freq (MHz)
1
10
FIGURE 16-13:
MAXIMUM IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, -40C to +85C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000 IDD (A)
100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
10 0.01
0.1 Freq (MHz)
1
10
DS30453D-page 124
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-14: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000 IDD (A)
100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
10 0.01
0.1 Freq (MHz)
1
FIGURE 16-15:
MAXIMUM IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, -40C to +85C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000 IDD (A)
100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V
10 0.01
0.1 Freq (MHz)
1
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 125
PIC16C5X
FIGURE 16-16: WDT TIMER TIME-OUT PERIOD vs. VDD(1) FIGURE 16-17: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
50 9000 45 8000
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Max -40C
40 7000 35 WDT period (ms) 6000 30 gm (A/W)
Max +85C
5000
Typ +25C
25
Max +70C
4000
20
Typ +25C
3000
Min +85C
15
MIn 0C
2000
10
MIn -40C
100 7.0
5 2.0
3.0
4.0
5.0
6.0
0 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts)
VDD (Volts) Note 1: Prescaler set to 1:1.
DS30453D-page 126
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-18: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD FIGURE 16-19: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
45
2500
40
Max -40C Max -40C
2000 35
30 1500 gm (A/V) gm (A/V) 25
Typ +25C Typ +25C
20
1000
15 500 10
Min +85C
Min +85C
5 0 0 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts) 2.0 3.0 4.0 5.0 6.0 7.0
VDD (Volts)
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 127
PIC16C5X
FIGURE 16-20: PORTA, B AND C IOH vs. VOH, VDD = 3V FIGURE 16-21: PORTA, B AND C IOH vs. VOH, VDD = 5V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
0
0
Min +85C
-5
Min +85C
-10
IOH (mA)
IOH (mA)
-10
Typ +25C
-20
Typ +25C
-15
Max -40C
-30
Max -40C
-20
-40 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (Volts) VOH (Volts) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DS30453D-page 128
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-22: PORTA, B AND C IOL vs. VOL, VDD = 3V FIGURE 16-23: PORTA, B AND C IOL vs. VOL, VDD = 5V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
45
90
Max -40C
40
80
Max -40C
35
70
30
60
Typ +25C
IOL (mA)
Typ +25C
20
IOL (mA)
25
50
40
Min +85C
15
Min +85C
30
10
20
5
10
0 0.0
0 0.5 1.0 1.5 VOL (Volts) 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts)
TABLE 16-2:
INPUT CAPACITANCE FOR PIC16C54A/C58A
Typical Capacitance (pF) 18L PDIP 18L SOIC 4.3 4.3 17.0 3.5 3.5 2.8
Pin RA port RB port MCLR OSC1 OSC2/CLKOUT T0CKI 5.0 5.0 17.0 4.0 4.3 3.2
All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 129
PIC16C5X
NOTES:
DS30453D-page 130
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
17.0 ELECTRICAL CHARACTERISTICS - PIC16C54C/CR54C/C55A/C56A/CR56A/ C57C/CR57C/C58B/CR58B
Absolute Maximum Ratings() Ambient temperature under bias............................................................................................................ -55C to +125C Storage temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.6V to (VDD + 0.6V) Total power dissipation(1) .....................................................................................................................................800 mW Max. current out of VSS pin ...................................................................................................................................150 mA Max. current into VDD pin ......................................................................................................................................100 mA Max. current into an input pin (T0CKI only) ..................................................................................................................... 500 A Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Max. output current sunk by any I/O pin .................................................................................................................25 mA Max. output current sourced by any I/O pin ............................................................................................................20 mA Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA Max. output current sunk by a single I/O (Port A, B or C) .......................................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 131
PIC16C5X
FIGURE 17-1: PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH, 0C TA +70C (COMMERCIAL TEMPS)
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 20 25
FIGURE 17-2:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0
PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH, -40C TA < 0C, +70C < TA +125C (OUTSIDE OF COMMERCIAL TEMPS)
4
10 Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
DS30453D-page 132
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 17-3:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 20 25
PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH, 0C TA +85C
FIGURE 17-4:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.7 2.5 2.0 0
PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH, -40C TA 0C
4
10 Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 133
PIC16C5X
17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
PIC16LC5X PIC16LCR5X (Commercial, Industrial) PIC16C5X PIC16CR5X (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial
Param Symbol No.
VDD D001
Characteristic/Device
Supply Voltage PIC16LC5X
Min
Typ Max Units
Conditions
2.5 2.7 2.5 3.0 4.5
-- -- -- -- -- 1.5* VSS --
5.5 5.5 5.5 5.5 5.5 -- -- --
V V V V V V V V/ms
-40C TA + 85C, 16LCR5X -40C TA 0C, 16LC5X 0C TA + 85C 16LC5X RC, XT, LP and HS mode from 0 - 10 MHz from 10 - 20 MHz Device in SLEEP mode See Section 5.1 for details on Power-on Reset See Section 5.1 for details on Power-on Reset
PIC16C5X D001A D002 D003 D004 Legend: VDR VPOR SVDD RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset
-- -- 0.05*
Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested.
*
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 134
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
PIC16LC5X PIC16LCR5X (Commercial, Industrial) PIC16C5X PIC16CR5X (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial
Param Symbol No.
IDD D010
Characteristic/Device
Supply Current(2,3) PIC16LC5X
Min
Typ Max Units
Conditions
-- -- --
0.5 11 14
2.4 27 35
mA A A
FOSC = 4.0 MHz, VDD = 5.5V, XT and RC modes FOSC = 32 kHz, VDD = 2.5V, LP mode, Commercial FOSC = 32 kHz, VDD = 2.5V, LP mode, Industrial FOSC = 4 MHz, VDD = 5.5V, XT and RC modes FOSC = 10 MHz, VDD = 3.0V, HS mode FOSC = 20 MHz, VDD = 5.5V, HS mode FOSC = 32 kHz, VDD = 3.0V, LP mode, Commercial FOSC = 32 kHz, VDD = 3.0V, LP mode, Industrial
D010A
PIC16C5X
-- -- -- -- --
1.8 2.6 4.5 14 17
2.4 3.6* 16 32 40
mA mA mA A A
Legend:
Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested.
*
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 135
PIC16C5X
17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
PIC16LC5X PIC16LCR5X (Commercial, Industrial) PIC16C5X PIC16CR5X (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial
Param Symbol No.
IPD D020
Characteristic/Device
Power-down Current(2) PIC16LC5X
Min
Typ Max Units
Conditions
-- -- -- -- -- -- -- -- -- -- -- --
0.25 0.25 1 1.25 0.25 0.25 1.8 2.0 4 4 9.8 12
2 3 5 8 4.0 5.0 7.0* 8.0* 12* 14* 27* 30*
A A A A A A A A A A A A
VDD = 2.5V, WDT disabled, Commercial VDD = 2.5V, WDT disabled, Industrial VDD = 2.5V, WDT enabled, Commercial VDD = 2.5V, WDT enabled, Industrial VDD = 3.0V, WDT disabled, Commercial VDD = 3.0V, WDT disabled, Industrial VDD = 5.5V, WDT disabled, Commercial VDD = 5.5V, WDT disabled, Industrial VDD = 3.0V, WDT enabled, Commercial VDD = 3.0V, WDT enabled, Industrial VDD = 5.5V, WDT enabled, Commercial VDD = 5.5V, WDT enabled, Industrial
D020A
PIC16C5X
Legend:
Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested.
*
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453D-page 136
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
17.2 DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E (Extended) PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C for extended
PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended) Param Symbol No. D001 VDD Characteristic Supply Voltage
Min
Typ
Max Units
Conditions RC, XT, LP, and HS mode from 0 - 10 MHz from 10 - 20 MHz Device in SLEEP mode See Section 5.1 for details on Power-on Reset
3.0 4.5 D002 D003 D004 D010 VDR VPOR SVDD IDD RAM Data Retention Voltage(1) VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Supply Current(2) XT and RC(3) modes HS mode Power-down Current(2) -- -- 0.05*
-- -- 1.5* Vss --
5.5 5.5 -- -- --
V V V V
V/ms See Section 5.1 for details on Power-on Reset mA mA
A A A A A A
-- -- -- -- -- -- -- --
1.8 9.0 0.3 10 12 4.8 18 26
3.3 20 17 50* 60* 31* 68* 90*
FOSC = 4.0 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V VDD = 3.0V, WDT disabled VDD = 4.5V, WDT disabled VDD = 5.5V, WDT disabled VDD = 3.0V, WDT enabled VDD = 4.5V, WDT enabled VDD = 5.5V, WDT enabled
D020
IPD
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 137
PIC16C5X
17.3 DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial, Extended)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial, Extended) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS
Param Symbol No. D030 VIL
Characteristic Input Low Voltage I/O Ports I/O Ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Input High Voltage I/O ports I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs Input Leakage Current(1,2) I/O ports MCLR MCLR T0CKI OSC1
VSS VSS VSS VSS VSS VSS 2.0 0.25 VDD+0.8 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD 0.15 VDD*
-- -- -- -- -- -- -- -- -- -- -- -- --
0.8 V 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD VDD VDD VDD VDD VDD VDD --
V V V V V V V V V V V V V
4.5V D040
VIH
D050 D060
VHYS IIL
-1.0 -5.0 -3.0 -3.0
0.5 -- 0.5 0.5 0.5
+1.0 +5.0 +3.0 +3.0 --
A A A A A
For VDD 5.5V: VSS VPIN VDD, pin at hi-impedance VPIN = VSS +0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP modes IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, RC mode only IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, RC mode only
D080
VOL
Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage(2) I/O ports OSC2/CLKOUT
-- --
-- --
0.6 0.6
V V
D090
VOH
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode.
DS30453D-page 138
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
17.4 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
mc osc os t0 wdt
MCLR oscillator OSC1 T0CKI watchdog timer
P R V Z
Period Rise Valid Hi-impedance
FIGURE 17-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B-04, 20
Pin CL VSS
CL = 50 pF 0 -15 pF
for all pins and OSC2 for RC mode for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 139
PIC16C5X
17.5 Timing Diagrams and Specifications
EXTERNAL CLOCK TIMING - PIC16C5X, PIC16CR5X
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
FIGURE 17-6:
TABLE 17-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic External CLKIN Frequency(1) Min DC DC DC DC Oscillator Frequency
(1)
AC Characteristics
Param No.
Symbol FOSC
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max Units 4.0 4.0 20 200 4.0 4.0 4.0 20 200 -- -- -- -- -- 2,200 250 250 200
Conditions
MHz XT OSC mode MHz HS OSC mode (04) MHz HS OSC mode (20) kHz LP OSC mode MHz RC OSC mode MHz XT OSC mode MHz HS OSC mode (04) MHz HS OSC mode (20) kHz LP OSC mode ns ns ns s ns ns ns ns s XT OSC mode HS OSC mode (04) HS OSC mode (20) LP OSC mode RC OSC mode XT OSC mode HS OSC mode (04) HS OSC mode (20) LP OSC mode
DC 0.45 4.0 4.0 5.0
1
TOSC
External CLKIN
Period(1)
250 250 50 5.0
Oscillator Period
(1)
250 250 250 50 5.0
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 140
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
TABLE 17-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic Instruction Cycle Time(2) Min -- 50* 20* 2.0* 4 TosR, TosF Clock in (OSC1) Rise or Fall Time -- -- -- * These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Typ 4/FOSC -- -- -- -- -- -- Max Units -- -- -- -- 25* 25* 50* -- ns ns s ns ns ns XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator LP oscillator Conditions
AC Characteristics
Param No. 2 3
Symbol Tcy
TosL, TosH Clock in (OSC1) Low or High Time
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 141
PIC16C5X
FIGURE 17-7: CLKOUT AND I/O TIMING - PIC16C5X, PIC16CR5X
Q4 OSC1 10 11 Q1 Q2 Q3
CLKOUT 13 I/O Pin (input) 17 I/O Pin (output) Old Value 15 New Value 18 12 16
14
19
20, 21 Note: Refer to Figure 17-5 for load conditions.
TABLE 17-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Characteristic OSC1 to CLKOUT(1) OSC1 to CLKOUT CLKOUT rise time
(1) (1)
AC Characteristics
Param No. 10 11 12 13 14 15 16 17 18 19 20 21 *
Symbol TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF
Min -- -- -- --
Typ 15 15 5.0 5.0 -- -- -- -- -- -- 10 10
Max 30** 30** 15** 15** 40** -- -- 100* -- -- 25** 25**
Units ns ns ns ns ns ns ns ns ns ns ns ns
CLKOUT fall time(1) CLKOUT to Port out valid
(1) (1)
-- 0.25 TCY+30* 0* -- TBD TBD -- --
Port in valid before CLKOUT Port in hold after CLKOUT
(1)
OSC1 (Q1 cycle) to Port out valid(2) OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time(2) Port output fall time
(2)
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Refer to Figure 17-5 for load conditions.
DS30453D-page 142
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 17-8: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X, PIC16CR5X
VDD MCLR 30 Internal POR 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 I/O pin (Note 1) 34
32
32
Note 1: Please refer to Figure 17-5 for load conditions.
TABLE 17-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial AC Characteristics -40C TA +85C for industrial -40C TA +125C for extended Param No. 30 31 32 34 * Symbol TmcL Twdt TDRT TioZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Device Reset Timer Period I/O Hi-impedance from MCLR Low Min 1000* 9.0* 9.0* 100* Typ -- 18* 18* 300* Max -- 30* 30* 1000* Units ns ms ms ns Conditions VDD = 5.0V VDD = 5.0V (Comm) VDD = 5.0V (Comm)
These parameters are characterized but not tested.
Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 143
PIC16C5X
FIGURE 17-9: TIMER0 CLOCK TIMINGS - PIC16C5X, PIC16CR5X
T0CKI 40 41
42 Note: Please refer to Figure 17-5 for load conditions.
TABLE 17-4:
TIMER0 CLOCK REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
AC Characteristics
Param Symbol Characteristic No. 40 Tt0H T0CKI High Pulse Width - No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width - No Prescaler - With Prescaler 42 Tt0P T0CKI Period
0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N
-- -- -- -- --
-- -- -- -- --
ns ns ns ns ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30453D-page 144
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
18.0 DEVICE CHARACTERIZATION - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/ CR57C/C58B/CR58B
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. "Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 18-1:
FOSC FOSC (25C) 1.10 1.08 1.06 1.04 1.02 1.00 0.98
TYPICAL RC OSCILLATOR FREQUENCY VS. TEMPERATURE
Frequency normalized to +25C
REXT 10 kW CEXT = 100 pF
VDD = 5.5V 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 T(C) 40 50 60 70
TABLE 18-1:
CEXT 20 pF
RC OSCILLATOR FREQUENCIES
REXT 3.3K 5K 10K 100K 5 MHz 3.8 MHz 2.2 MHz 262 kHz 1.63 MHz 1.2 MHz 684 kHz 71 kHz 660 kHz 484 kHz 267 kHz 29 kHz Average Fosc @ 5V, 25C 27% 21% 21% 31% 13% 13% 18% 25% 10% 14% 15% 19%
100 pF
3.3K 5K 10K 100K
300 pF
3.3K 5.0K 10K 100K
The frequencies are measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 145
PIC16C5X
FIGURE 18-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25C
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
6 R=3.3K 5 R=5K 4
3 R=10K 2
1
R=100K 0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
FIGURE 18-3:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
1.8 R=3.3K 1.6
1.4 FOSC (MHz) R=5K 1.0
R=10K 0.6
0.2 R=100K 0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6 6.0
DS30453D-page 146
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25C
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
700 R=3.3K 600
500 R=5K FOSC (kHz)
400
300 R=10K
200
100 R=100K 0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
FIGURE 18-5:
TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
25
20
15 IPD (uA) 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 147
PIC16C5X
FIGURE 18-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
25
20
15 IPD (uA) 10 5.0 0
2.5
3.0
3.5
4.0 VDD (Volts)
4.5
5.0
5.5
6.0
FIGURE 18-7:
TYPICAL IPD vs. VDD, WATCHDOG ENABLED (-40C, 85C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
35
30
25
20 IPD (uA)
15
10
5.0
(-40C)
(+85C)
0 2.5 3.0
3.5
4.0 VDD (Volts)
4.5
5.0
5.5
6.0
DS30453D-page 148
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-8: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
2.0 1.8 1.6 VTH (Volts) 1.4 1.2 1.0 0.8 0.6
25 Typ (+ C )
2.5
3.0
3.5
4.0
4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 18-9:
VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
4.5 4.0 3.5 VIH, VIL (Volts) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 Note: 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
VIL max (-40 C to +85C)
C) +85 C to (-40 max VIH C + 25 ) typ VIH 85C to + 0C (-4 min VIH
VIL typ +25C
VIL min (-40C to +85 C)
These input pins have Schmitt Trigger input buffers.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 149
PIC16C5X
FIGURE 18-10: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT (IN XT, HS AND LP MODES) vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
3.4 3.2 3.0 2.8 2.6 VTH (Volts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
(+ Typ 25C )
FIGURE 18-11:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C)
TYPICAL IDD vs FREQ(RC MODE @ 20pF/25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000 IDD(A)
100
5.5V 4.5V 3.5V 2.5V
10
0.1
1 FREQ(MHz)
10
DS30453D-page 150
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-12: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25C)
TYPICAL IDD vs FREQ(RC MODE @ 100 pF/25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000
IDD(A)
100
5.5V 4.5V 3.5V 2.5V
10 0.1 1 FREQ(MHz) 10
FIGURE 18-13:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C)
TYPICAL IDD vs FREQ (RC MODE @ 300 pF/25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
10000
1000
IDD(A)
100
5.5V 4.5V 3.5V 2.5V
10 0.01
0.1 FREQ(MHz)
1
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 151
PIC16C5X
FIGURE 18-14: WDT TIMER TIME-OUT PERIOD vs. VDD(1) FIGURE 18-15: PORTA, B AND C IOH vs. VOH, VDD = 3 V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
50
0
45 -5 40 Min +85C
35 WDT period (ms) IOH (mA) -10
30 Typ +125C Typ +85C 20 Typ +25C 15 Typ -40C 10
Typ +25C -15 Max -40C -20
25
-25 0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (Volts) 5.0 6.0 7.0
5.0 2.0
3.0
4.0
VDD (Volts)
Note 1: Prescaler set to 1:1.
DS30453D-page 152
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-16: PORTA, B AND C IOH vs. VOH, VDD = 5 V FIGURE 18-17: PORTA, B AND C IOL vs. VOL, VDD = 3 V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
0
45 Max -40C
40
-10
35
Typ +125C IOH (mA)
30
Typ +85C Typ +25C Typ -40C
IOL (mA)
-20
25 Typ +25C 20
-30
15 Min +85C 10
-40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOH (Volts)
5
0 0.0
0.5
1.0
1.5 VOL (Volts)
2.0
2.5
3.0
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 153
PIC16C5X
FIGURE 18-18: PORTA, B AND C IOL vs. VOL, VDD = 5 V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
90
80
Max -40C
70
60 Typ +25C IOL (mA) 50
40 Min +85C 30
20
10
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts)
TABLE 18-2:
Pin
INPUT CAPACITANCE
Typical Capacitance (pF) 18L PDIP 18L SOIC 4.3 4.3 17.0 3.5 3.5 2.8
RA port RB port MCLR OSC1 OSC2/CLKOUT T0CKI
5.0 5.0 17.0 4.0 4.3 3.2
All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account.
DS30453D-page 154
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
19.0 ELECTRICAL CHARACTERISTICS - PIC16C54C/C55A/C56A/C57C/C58B 40MHz
Absolute Maximum Ratings() Ambient temperature under bias............................................................................................................ -55C to +125C Storage temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.6V to (VDD + 0.6V) Total power dissipation(1) .....................................................................................................................................800 mW Max. current out of VSS pin ...................................................................................................................................150 mA Max. current into VDD pin ......................................................................................................................................100 mA Max. current into an input pin (T0CKI only) ..................................................................................................................... 500 A Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Max. output current sunk by any I/O pin .................................................................................................................25 mA Max. output current sourced by any I/O pin ............................................................................................................20 mA Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA Max. output current sunk by a single I/O (Port A, B or C) .......................................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 155
PIC16C5X
FIGURE 19-1:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 3: Operation between 20 to 40 MHz requires the following: * VDD between 4.5V. and 5.5V * OSC1 externally driven * OSC2 not connected * HS mode * Commercial temperatures Devices qualified for 40 MHz operation have -40 designation (ex: PIC16C54C-40/P). 4: For operation between DC and 20 MHz, see Section 17.1. 20 25 40
PIC16C54C/C55A/C56A/C57C/C58B-40 VOLTAGE-FREQUENCY GRAPH, 0C TA +70C
DS30453D-page 156
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
19.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial) (1)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial Min 4.5
(2)
PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial) Param Symbol No. D001 D002 D003 D004 D010 D020 VDD VDR VPOR SVDD IDD IPD Characteristic Supply Voltage RAM Data Retention Voltage VDD Start Voltage to ensure Power-on Reset
Typ -- 1.5* Vss -- 5.2 6.8 1.8 9.8
Max Units 5.5 -- -- -- 12.3 16 7.0 27* V V V
Conditions HS mode from 20 - 40 MHz Device in SLEEP mode See Section 5.1 for details on Power-on Reset
-- --
VDD Rise Rate to ensure Power- 0.05* on Reset Supply Current(3) Power-down Current(3) -- -- -- --
V/ms See Section 5.1 for details on Power-on Reset mA mA A A FOSC = 40 MHz, VDD = 4.5V, HS mode FOSC = 40 MHz, VDD = 5.5V, HS mode VDD = 5.5V, WDT disabled, Commercial VDD = 5.5V, WDT enabled, Commercial
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: Device operation between 20 MHz to 40 MHz requires the following: VDD between 4.5V to 5.5V, OSC1 pin externally driven, OSC2 pin not connected, HS oscillator mode and commercial temperatures. For operation between DC and 20 MHz, See Section 19.1. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 157
PIC16C5X
19.2 DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial)(1)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial Min Typ Max Units Conditions DC CHARACTERISTICS Param Symbol No. D030 VIL
Characteristic Input Low Voltage I/O Ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 Input High Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 Hysteresis of Schmitt Trigger inputs Input Leakage Current(2,3) I/O ports MCLR MCLR T0CKI OSC1
VSS VSS VSS VSS 2.0 0.85 VDD 0.85 VDD 0.8 VDD 0.15 VDD*
-- -- -- -- -- -- -- -- --
0.8 0.15 VDD 0.15 VDD 0.2 VDD VDD VDD VDD VDD --
V V V V V V V V V
4.5V D040
VIH
D050 D060
VHYS IIL
-1.0 -5.0 -- -3.0 -3.0 -- VDD - 0.7
0.5 -- 0.5 0.5 0.5 -- --
+1.0 +5.0 +3.0 +3.0 -- 0.6 --
A A A A A V V
For VDD 5.5V: VSS VPIN VDD, pin at hi-impedance VPIN = VSS +0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, HS IOL = 8.7 mA, VDD = 4.5V IOH = -5.4 mA, VDD = 4.5V
D080 D090 *
VOL VOH
Output Low Voltage I/O ports Output High I/O ports Voltage(3)
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: Device operation between 20 MHz to 40 MHz requires the following: VDD between 4.5V to 5.5V, OSC1 pin externally driven, OSC2 pin not connected and HS oscillator mode and commercial temperatures. For operation between DC and 20 MHz, See Section 17.3. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin.
DS30453D-page 158
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
19.3 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
mc osc os t0 wdt
MCLR oscillator OSC1 T0CKI watchdog timer
P R V Z
Period Rise Valid Hi-impedance
FIGURE 19-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS PIC16C54C/C55A/C56A/C57C/C58B-40
Pin CL VSS
CL = 50 pF for all pins except OSC2 0 pF for OSC2 in HS mode for operation between 20 MHz to 40 MHz
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 159
PIC16C5X
19.4 Timing Diagrams and Specifications
EXTERNAL CLOCK TIMING - PIC16C5X-40
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
FIGURE 19-3:
TABLE 19-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X-40
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial Characteristic External CLKIN Frequency(1) External CLKIN Period(1)
(2)
AC Characteristics Param No. Symbol FOSC 1 2 3 4 * TOSC Tcy
Min 20 25 -- 6.0* --
Typ -- -- 4/FOSC -- --
Max Units 40 -- -- -- 6.5*
Conditions
MHz HS OSC mode ns -- ns ns HS oscillator HS oscillator HS OSC mode
Instruction Cycle Time
TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time
These parameters are characterized but not tested.
Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 160
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 19-4: CLKOUT AND I/O TIMING - PIC16C5X-40
Q4 OSC1 10 11 Q1 Q2 Q3
CLKOUT 13 I/O Pin (input) 17 I/O Pin (output) Old Value 15 New Value 18 12 16
14
19
20, 21 . Note: Refer to Figure 19-2 for load conditions.
TABLE 19-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X-40
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial Characteristic OSC1 to CLKOUT(1,2) OSC1 to CLKOUT CLKOUT fall time
(1,2)
AC Characteristics Param No. 10 11 12 13 14 15 16 17 18 19 20 21 * Symbol TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF
Min -- -- -- --
Typ 15 15 5.0 5.0 -- -- -- -- -- -- 10 10
Max 30** 30** 15** 15** 40** -- -- 100 -- -- 25** 25**
Units ns ns ns ns ns ns ns ns ns ns ns ns
CLKOUT rise time(1,2)
(1,2) (1,2) (1,2)
CLKOUT to Port out valid
-- 0.25 TCY+30* 0* -- TBD TBD -- --
Port in valid before CLKOUT
Port in hold after CLKOUT(1,2) OSC1 (Q1 cycle) to Port out valid(2) OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time(2) Port output fall time
(2)
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Refer to Figure 19-2 for load conditions.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 161
PIC16C5X
FIGURE 19-5:
VDD MCLR 30 Internal POR 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 I/O pin(1) 34
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X-40
32
32
.Note 1: Please refer to Figure 19-2 for load conditions.
TABLE 19-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X-40
Standard Operating Conditions (unless otherwise specified) AC Characteristics Operating Temperature 0C TA +70C (commercial) Operating Voltage VDD range is described in Section 19.1. Param No. 30 31 32 34 * Symbol TmcL Twdt TDRT TioZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Device Reset Timer Period I/O Hi-impedance from MCLR Low Min 1000* 9.0* 9.0* 100* Typ -- 18* 18* 300* Max -- 30* 30* 1000* Units ns ms ms ns Conditions VDD = 5.0V VDD = 5.0V (Comm) VDD = 5.0V (Comm)
These parameters are characterized but not tested.
Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30453D-page 162
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 19-6: TIMER0 CLOCK TIMINGS - PIC16C5X-40
T0CKI 40 41
42 Note: Refer to Figure 19-2 for load conditions.
TABLE 19-4:
TIMER0 CLOCK REQUIREMENTS PIC16C5X-40
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C for commercial Min Typ Max Units Conditions
AC Characteristics Param No. 40 Symbol Characteristic Tt0H
T0CKI High Pulse Width - No Prescaler - With Prescaler
0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N
-- -- -- -- --
-- -- -- -- --
ns ns ns ns ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
41
Tt0L
T0CKI Low Pulse Width - No Prescaler - With Prescaler
42
Tt0P
T0CKI Period
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 163
PIC16C5X
NOTES:
DS30453D-page 164
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
20.0 DEVICE CHARACTERIZATION - PIC16C54C/C55A/C56A/C57C/C58B 40MHz
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. "Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 20-1:
TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
25
20
15 IPD (uA) 10 5.0 0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 165
PIC16C5X
FIGURE 20-2: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
25
20
15 IPD (uA) 10 5.0 0
2.5
3.0
3.5
4.0 VDD (Volts)
4.5
5.0
5.5
6.0
FIGURE 20-3:
TYPICAL IPD vs. VDD, WATCHDOG ENABLED (-40C, 85C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
35
30
25
20 IPD (uA)
15
10
5.0
(-40C)
(+85C)
0
2.5
3.0
3.5
4.0 VDD (Volts)
4.5
5.0
5.5
6.0
DS30453D-page 166
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 20-4: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
2.0 1.8 1.6 VTH (Volts) 1.4 1.2 1.0 0.8 0.6
2 Typ (+ 5 C )
2.5
3.0
3.5
4.0
4.5 VDD (Volts)
5.0
5.5
6.0
FIGURE 20-5:
VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT (HS MODE) vs. VDD
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
3.4 3.2 3.0 2.8 2.6 VTH (Volts) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0
(+ Typ ) 25 C
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 167
PIC16C5X
FIGURE 20-6: TYPICAL IDD vs. VDD (40 MHZ, WDT DISABLED, HS MODE, 70C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
12
11
10
9.0 IDD (mA)
8.0
7.0
6.0
5.0
4.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 6.0 6.5
DS30453D-page 168
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
FIGURE 20-7: WDT TIMER TIME-OUT PERIOD vs. VDD(1) FIGURE 20-8: IOH vs. VOH, VDD = 5 V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
0
50
45 -10 40 Typ +125C WDT period (ms) IOH (mA) 35
-20
30 Typ +125C Typ +85C 20 Typ +25C 15 Typ -40C 10
Typ +85C Typ +25C Typ -40C
25
-30
-40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOH (Volts)
5.0 2.0
3.0
4.0
5.0
6.0
7.0
VDD (Volts)
Note 1: Prescaler set to 1:1.
TABLE 20-1:
Pin
INPUT CAPACITANCE
Typical Capacitance (pF) 18L PDIP 18L SOIC 4.3 4.3 17.0 3.5 3.5 2.8
RA port RB port MCLR OSC1 OSC2/CLKOUT T0CKI
5.0 5.0 17.0 4.0 4.3 3.2
All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account.
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 169
PIC16C5X
FIGURE 20-9: IOL vs. VOL, VDD = 5 V
Typical: statistical mean @ 25C Maximum: mean + 3s (-40C to 125C) Minimum: mean - 3s (-40C to 125C)
90
80
Max -40C
70
60 Typ +25C IOL (mA) 50
40 Min +85C 30
20
10
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts)
DS30453D-page 170
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
21.0
21.1
PACKAGING INFORMATION
Package Marketing Information
Example
PIC16C56A -04I/P456 0023CBA XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
18-Lead PDIP
28-Lead Skinny PDIP (.300")
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16C55A -04I/SP456 0023CBA
28-Lead PDIP (.600")
XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN
Example
PIC16C55A -04/P126 0042CDA
18-Lead SOIC
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16C54C -04/S0218 0018CDK
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16C57C -04/SO 0015CBK
20-Lead SSOP
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example
PIC16C54C -04/SS218 0020CBP
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16C57C -04/SS123 0025CBK
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 171
PIC16C5X
Package Marking Information (Cont'd)
18-Lead CERDIP Windowed
XXXXXXXX XXXXXXXX YYWWNNN
Example
PIC16C54C /JW 0001CBA
28-Lead CERDIP Windowed
XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example
PIC16C57C /JW 0038CBA
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS30453D-page 172
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
18-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1
c
eB Units Dimension Limits n p
B
p
MIN
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .890 .898 .905 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007
INCHES* NOM 18 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 173
PIC16C5X
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1 B p
c eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN
INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095
Drawing No. C04-070
DS30453D-page 174
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Dual In-line (P) - 600 mil (PDIP)
E1
D
2 n E A c eB Units Dimension Limits n p INCHES* NOM 28 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 28 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 12.83 13.84 35.43 36.32 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 A2 L 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .505 .545 .560 Overall Length D 1.395 1.430 1.465 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .620 .650 .680 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-079
4.83 4.06 15.88 14.22 37.21 3.43 0.38 1.78 0.56 17.27 15 15
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 175
PIC16C5X
18-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E p E1
D
2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0
INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12
MAX
MIN
.104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15
MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12
MAX
2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051
DS30453D-page 176
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E E1 p
D
B n h 45 c A Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 177
PIC16C5X
20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n
2 1
c A
A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0
INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10
MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5
MAX
1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072
DS30453D-page 178
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n 2 1
A c A2
L
A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .396 .022 .004 0 .010 0 0
INCHES NOM 28 .026 .073 .068 .006 .309 .207 .402 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .319 .212 .407 .037 .010 8 .015 10 10
MILLIMETERS* NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.38 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page 179
PIC16C5X
18-Lead Ceramic Dual In-line with Window (JW) - 300 mil (CERDIP)
E1
W2
D
2 n W1 E 1
A c eB A1 B1 B Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB W1 W2 INCHES* NOM 18 .100 .183 .160 .023 .313 .290 .900 .138 .010 .055 .019 .385 .140 .200 p
A2
L
MIN
MAX
MIN
Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Width Window Length * Controlling Parameter Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010
.170 .155 .015 .300 .285 .880 .125 .008 .050 .016 .345 .130 .190
.195 .165 .030 .325 .295 .920 .150 .012 .060 .021 .425 .150 .210
MILLIMETERS NOM 18 2.54 4.32 4.64 3.94 4.06 0.38 0.57 7.62 7.94 7.24 7.37 22.35 22.86 3.18 3.49 0.20 0.25 1.27 1.40 0.41 0.47 8.76 9.78 3.30 3.56 4.83 5.08
MAX
4.95 4.19 0.76 8.26 7.49 23.37 3.81 0.30 1.52 0.53 10.80 3.81 5.33
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(c) 2002 Microchip Technology Inc.
PIC16C5X
28-Lead Ceramic Dual In-line with Window (JW) - 600 mil (CERDIP)
E1
W
D
2 n 1
E
A c eB A1 B1 B INCHES* NOM 28 .100 .210 .160 .038 .600 .520 1.460 .138 .010 .058 .020 .660 .280 p MILLIMETERS NOM 28 2.54 4.95 5.33 3.94 4.06 0.38 0.95 15.11 15.24 13.06 13.21 36.32 37.08 3.18 3.49 0.20 0.25 1.27 1.46 0.41 0.51 15.49 16.76 6.86 7.11
A2 L
Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Diameter * Controlling Parameter Significant Characteristic JEDEC Equivalent: MO-103 Drawing No. C04-013
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB W
MIN
MAX
MIN
MAX
.195 .155 .015 .595 .514 1.430 .125 .008 .050 .016 .610 .270
.225 .165 .060 .625 .526 1.490 .150 .012 .065 .023 .710 .290
5.72 4.19 1.52 15.88 13.36 37.85 3.81 0.30 1.65 0.58 18.03 7.37
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PIC16C5X
NOTES:
DS30453D-page 182
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(c) 2002 Microchip Technology Inc.
PIC16C5X
APPENDIX A: COMPATIBILITY
To convert code written for PIC16CXX to PIC16C5X, the user should take the following steps: 1. Check any CALL, GOTO or instructions that modify the PC to determine if any program memory page select operations (PA2, PA1, PA0 bits) need to be made. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any special function register page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change RESET vector to proper value for processor used. Remove any use of the ADDLW, RETURN and SUBLW instructions. Rewrite any code segments that use interrupts.
2.
3.
4. 5. 6. 7.
(c) 2002 Microchip Technology Inc.
Preliminary
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PIC16C5X
NOTES:
DS30453D-page 184
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(c) 2002 Microchip Technology Inc.
PIC16C5X
INDEX A
Absolute Maximum Ratings PIC16C54/55/56/57 .................................................... 67 PIC16C54A ............................................................... 103 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B ............................................................ 131 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B-40 ....................................................... 155 PIC16CR54A .............................................................. 79 ADDWF ............................................................................... 51 ALU ....................................................................................... 9 ANDLW ............................................................................... 51 ANDWF ............................................................................... 51 Applications........................................................................... 5 Architectural Overview .......................................................... 9 Assembler MPASM Assembler ..................................................... 61 PIC16CR54A Commercial .................................................. 80, 83 Extended ...................................................... 82, 84 Industrial ....................................................... 80, 83 PIC16LV54A Commercial .............................................. 108, 109 Industrial ................................................... 108, 109 DECF .................................................................................. 54 DECFSZ ............................................................................. 54 Development Support ......................................................... 61 Device Characterization PIC16C54/55/56/57/CR54A ....................................... 91 PIC16C54A............................................................... 117 PIC16C54C/C55A/C56A/C57C/C58B-40 ................. 165 Device Reset Timer (DRT) ................................................. 23 Device Varieties.................................................................... 7 Digit Carry (DC) bit ......................................................... 9, 29 DRT .................................................................................... 23
E
Electrical Specifications PIC16C54/55/56/57 .................................................... 67 PIC16C54A............................................................... 103 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B ............................................................ 131 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B-40....................................................... 155 PIC16CR54A .............................................................. 79 Errata .................................................................................... 3 External Power-On Reset Circuit........................................ 21
B
Block Diagram On-Chip Reset Circuit ................................................. 20 PIC16C5X Series........................................................ 10 Timer0 ......................................................................... 37 TMR0/WDT Prescaler................................................. 41 Watchdog Timer .......................................................... 46 Brown-Out Protection Circuit .............................................. 23 BSF ..................................................................................... 52 BTFSC ................................................................................ 52 BTFSS ................................................................................ 52
F
Family of Devices PIC16C5X..................................................................... 6 FSR Register ...................................................................... 33 Value on reset............................................................. 20
C
CALL ............................................................................. 31, 53 Carry (C) bit .................................................................... 9, 29 Clocking Scheme ................................................................ 13 CLRF................................................................................... 53 CLRW ................................................................................. 53 CLRWDT............................................................................. 53 CMOS Technology................................................................ 1 Code Protection ............................................................ 43, 47 COMF ................................................................................. 54 Compatibility ..................................................................... 183 Configuration Bits................................................................ 44
G
General Purpose Registers Value on reset............................................................. 20 GOTO ........................................................................... 31, 55
H
High-Performance RISC CPU .............................................. 1
D
Data Memory Organization ................................................. 26 DC Characteristics PIC16C54/55/56/57 Commercial................................................... 68, 71 Extended....................................................... 70, 72 Industrial ....................................................... 69, 71 PIC16C54A Commercial............................................... 104, 109 Extended................................................... 106, 109 Industrial ................................................... 104, 109 PIC16C54C/C55A/C56A/C57C/C58B-40 Commercial............................................... 157, 158 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B Commercial............................................... 134, 138 Extended................................................... 137, 138 Industrial ................................................... 134, 138
I
I/O Interfacing ..................................................................... 35 I/O Ports ............................................................................. 35 I/O Programming Considerations ....................................... 36 ICEPIC In-Circuit Emulator ................................................. 62 ID Locations.................................................................. 43, 47 INCF ................................................................................... 55 INCFSZ............................................................................... 55 INDF Register ..................................................................... 33 Value on reset............................................................. 20 Indirect Data Addressing .................................................... 33 Instruction Cycle ................................................................. 13 Instruction Flow/Pipelining .................................................. 13 Instruction Set Summary .................................................... 49 IORLW ................................................................................ 56 IORWF................................................................................ 56
K
KeeLoq Evaluation and Programming Tools ...................... 64
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PIC16C5X
L
Loading of PC ..................................................................... 31 Program Memory Organization........................................... 25 Program Verification/Code Protection ................................ 47
M
MCLR Reset Register values on ...................................................... 20 Memory Map PIC16C54/CR54/C55.................................................. 25 PIC16C56/CR56 ......................................................... 25 PIC16C57/CR57/C58/CR58 ....................................... 25 Memory Organization.......................................................... 25 MOVF.................................................................................. 56 MOVLW............................................................................... 56 MOVWF .............................................................................. 57 MPLAB C17 and MPLAB C18 C Compilers........................ 61 MPLAB ICD In-Circuit Debugger......................................... 63 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE.................................................................. 62 MPLAB Integrated Development Environment Software .... 61 MPLINK Object Linker/MPLIB Object Librarian .................. 62
Q
Q cycles .............................................................................. 13 Quick-Turnaround-Production (QTP) Devices...................... 7
R
RC Oscillator....................................................................... 17 Read Only Memory (ROM) Devices ..................................... 7 Read-Modify-Write.............................................................. 36 Register File Map PIC16C54, PIC16CR54, PIC16C55, PIC16C56, PIC16CR56 ................................................................ 26 PIC16C57/CR57 ......................................................... 27 PIC16C58/CR58 ......................................................... 27 Registers Special Function ......................................................... 28 Value on reset............................................................. 20 Reset .................................................................................. 19 Reset on Brown-Out ........................................................... 23 RETLW ............................................................................... 57 RLF ..................................................................................... 58 RRF .................................................................................... 58
N
NOP .................................................................................... 57
O
One-Time-Programmable (OTP) Devices............................. 7 OPTION .............................................................................. 57 OPTION Register ................................................................ 30 Value on reset ............................................................. 20 Oscillator Configurations ..................................................... 15 Oscillator Types HS ............................................................................... 15 LP................................................................................ 15 RC ............................................................................... 15 XT ............................................................................... 15
S
Serialized Quick-Turnaround-Production (SQTP) Devices... 7 SLEEP .................................................................... 43, 47, 58 Software Simulator (MPLAB SIM) ...................................... 62 Special Features of the CPU .............................................. 43 Special Function Registers ................................................. 28 Stack................................................................................... 32 STATUS Register ........................................................... 9, 29 Value on reset............................................................. 20 SUBWF............................................................................... 59 SWAPF ............................................................................... 59
P
PA0 bit................................................................................. 29 PA1 bit................................................................................. 29 Paging ................................................................................. 31 PC ....................................................................................... 31 Value on reset ............................................................. 20 PD bit ............................................................................ 19, 29 Peripheral Features............................................................... 1 PICDEM 1 Low Cost PICmicro Demonstration Board ........ 63 PICDEM 17 Demonstration Board ...................................... 64 PICDEM 2 Low Cost PIC16CXX Demonstration Board...... 63 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ... 64 PICSTART Plus Entry Level Development Programmer .... 63 Pin Configurations................................................................. 2 Pinout Description - PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, PIC16CR58 ................................. 11 Pinout Description - PIC16C55, PIC16C57, PIC16CR57 ... 12 PORTA................................................................................ 35 Value on reset ............................................................. 20 PORTB................................................................................ 35 Value on reset ............................................................. 20 PORTC................................................................................ 35 Value on reset ............................................................. 20 Power-Down Mode.............................................................. 47 Power-On Reset (POR) ...................................................... 21 Register values on ...................................................... 20 Prescaler ............................................................................. 40 PRO MATE II Universal Device Programmer ..................... 63 Program Counter................................................................. 31
T
Timer0 Switching Prescaler Assignment ................................ 40 Timer0 (TMR0) Module............................................... 37 TMR0 register - Value on reset................................... 20 TMR0 with External Clock .......................................... 39 Timing Diagrams and Specifications PIC16C54/55/56/57 .................................................... 74 PIC16C54A............................................................... 111 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B ............................................................ 140 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B-40 ....................................................... 160 PIC16CR54A .............................................................. 86 Timing Parameter Symbology and Load Conditions PIC16C54/55/56/57 .................................................... 73 PIC16C54A............................................................... 110 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B ............................................................ 139 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ C58B/CR58B-40 ....................................................... 159 PIC16CR54A .............................................................. 85 TO bit ............................................................................ 19, 29 TRIS.................................................................................... 59 TRIS Registers ................................................................... 35 Value on reset............................................................. 20
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PIC16C5X
U
UV Erasable Devices ............................................................ 7
W
W Register Value on reset ............................................................. 20 Wake-up from SLEEP ................................................... 19, 47 Watchdog Timer (WDT) ................................................ 43, 46 Period.......................................................................... 46 Programming Considerations ..................................... 46 Register values on reset ............................................. 20 WWW, On-Line Support ....................................................... 3
X
XORLW ............................................................................... 60 XORWF............................................................................... 60
Z
Zero (Z) bit ...................................................................... 9, 29
(c) 2002 Microchip Technology Inc.
Preliminary
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NOTES:
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Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world.
013001
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
(c) 2002 Microchip Technology Inc.
Preliminary
DS30453D-page189
PIC16C5X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C5X Questions: 1. What are the best features of this document? Y N Literature Number: DS30453D FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30453D-page190
Preliminary
(c) 2002 Microchip Technology Inc.
PIC16C5X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX Frequency Range/OSC Type
PIC16C54 PIC16C54A PIC16CR54A PIC16C54C PIC16CR54C PIC16C55 PIC16C55A PIC16C56 PIC16C56A PIC16CR56A PIC16C57 PIC16C57C PIC16CR57C PIC16C58B PIC16CR58B
X Temperature Range
/XX Package
XXX Pattern
Examples:
a) PIC16C55A - 04/P 301 = Commercial Temp., PDIP package, 4 MHz, standard VDD limits, QTP pattern #301 PIC16LC54C - 04I/SO Industrial Temp., SOIC package, 200 kHz, extended VDD limits PIC16C57 - RC/SP = RC Oscillator, commercial temp, skinny PDIP package, 4 MHz, standard VDD limits
b) Device PIC16C54T(2) PIC16C54AT(2) PIC16CR54AT(2) PIC16C54CT(2) PIC16CR54CT(2) PIC16C55T(2) PIC16C55AT(2) PIC16C56T(2) PIC16C56AT(2) PIC16CR56AT(2) PIC16C57T(2) PIC16C57CT(2) PIC16CR57CT(2) PIC16C58BT(2) PIC16CR58BT(2) c)
d)
PIC16C58BT -40/SS 123 = commercial temp, SSOP package in tape and reel, 4 MHz, extended VDD limits, ROM pattern #123
Note
1: 2:
Frequency Range/ Oscillator Type
RC LP XT HS 02 04 10 20 40 b(4)
Resistor Capacitor Low Power Crystal Standard Crystal/Resonator High Speed Crystal 200 KHz (LP) or 2 MHz (XT and RC) 200 KHz (LP) or 4 MHz (XT and RC) 10 MHz (HS only) 20 MHz (HS only) 40 MHz (HS only) No oscillator type for JW packages(3)
3:
4:
C = normal voltage range LC = extended T = in tape and reel - SOIC and SSOP packages only JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirements of each oscillator type, including LC devices. b = Blank
*RC/LP/XT/HS are for 16C54/55/56/57 devices only -02 is available for 16LV54A only -04/10/20 options are available for all other devices -40 is available for 16C54C/55A/56A/57C/58B devices only b(4) = I = E =
Temperature Range
0C to -40C to -40C to
+70C +85C +125C
Package
S = JW = P SO SS SP = = = =
Die in Waffle Pack 28-pin 600 mil/18-pin 300 mil windowed CERDIP(3) 28-pin 600 mil/18-pin 300 mil PDIP 300 mil SOIC 209 mil SSOP 28-pin 300 mil Skinny PDIP
*See Section 21 for additional package information.
Pattern
QTP, SQTP, ROM code (factory specified) or Special Requirements. Blank for OTP and Windowed devices.
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
(c) 2002 Microchip Technology Inc.
Preliminary
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WORLDWIDE SALES AND SERVICE
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03/01/02
DS30453D-page 192
(c) 2002 Microchip Technology Inc.

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